DS578F3
15
CS8416
RXP0
RXP1
RXP2
RXP3
RXP4
RXP5
RXP6
RXP7
1
28
27
26
7
8
9
10
Positive AES3/SPDIF Input (Input) - Single-ended or differential receiver inputs carrying AES3 or
S/PDIF encoded digital data. The RXP[7:0] inputs comprise the 8:2 S/PDIF Input Multiplexer. The select
line control is accessed using the Control 4 register (04h). Unused multiplexer inputs should be left float-
ommended input circuits.
RXN
2
Negative AES3/SPDIF Input (Input) - Single-ended or differential receiver input carrying AES3 or
S/PDIF encoded digital data. Used along with RXP[7:0] to form an AES3 differential input. In single-
ended operation this should be AC coupled to ground through a capacitor. See
“ExternalOMCK
22
System Clock (Input) - When the OMCK System Clock Mode is enabled using the SWCLK bit in the
Control 1 register, the clock signal input on this pin is automatically output through RMCK on PLL unlock.
OMCK serves as the reference signal for OMCK/RMCK ratio expressed in register 18h.
“OMCK SystemRMCK
21
Input Section Recovered Master Clock (Output) - Input section recovered master clock output from
the PLL. Frequency defaults to 256x the sample rate (Fs) and may be set to 128x through the RMCKF bit
in the Control 1 register (01h). RMCK may also be set to high impedance by the RXD bit in the Control 4
register (04h).
OSCLK
24
Serial Audio Output Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT pin
OLRCK
25
Serial Audio Output Left/Right Clock (Input/Output) - Word rate clock for the audio data on the
SDOUT pin. Frequency will be the output sample rate (Fs)
SDOUT
23
Serial Audio Output Data (Output) - Audio data serial output pin. This pin must be pulled high to VL
through a 47 k
Ω resistor to place the part in Software Mode.
SDA /
CDOUT
14
Serial Control Data I/O (IC) / Data Out (SPI) (Input/Output) - In IC Mode, SDA is the control I/O data
line. SDA is open drain and requires an external pull-up resistor to VL. In SPI Mode, CDOUT is the out-
SCL /
CCLK
13
Control Port Clock (Input) - Serial control interface clock and is used to clock control data bits into and
out of the CS8416. CCLK is an open drain output and requires an external pull-up resistor to VL. See the
AD0 / CS
11
Address Bit 0 (IC) / Control Port Chip Select (SPI) (Input) - A falling edge on this pin puts the CS8416
into SPI Control Port Mode. With no falling edge, the CS8416 defaults to IC Mode. In IC Mode, AD0 is
a chip address pin. In SPI Mode, CS is used to enable the control port interface on the CS8416. See the
AD1 /
CDIN
12
Address Bit 1 (IC) / Serial Control Data in (SPI) (Input) - In IC Mode, AD1 is a chip address pin. In
AD2 /
GPO2
15
General Purpose Output 2 (Output) - If using the IC control port, this pin must be pulled high or low
through a 47 k
GPO1
16
GPO0
17
THERMAL
PAD
-
Thermal Pad - Thermal relief pad for optimized heat dissipation.
Pin
Name
Pin #
Pin Description