參數(shù)資料
型號(hào)： CS8416-DZZ
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 18/37頁(yè)
文件大?。?/td> 0K
描述： IC RCVR DGTL 192KHZ 28TSSOP AUTO
標(biāo)準(zhǔn)包裝： 50
類(lèi)型： 數(shù)字音頻接口接收器
應(yīng)用： 數(shù)字音頻
安裝類(lèi)型： 表面貼裝
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 28-TSSOP
包裝： 管件
產(chǎn)品目錄頁(yè)面： 759 (CN2011-ZH PDF)
配用： 598-1017-ND - BOARD EVAL FOR CS8416 RCVR
其它名稱(chēng)： 598-1726
DS578F3
25
CS8416
7.1
Slip/Repeat Behavior
When using the serial audio output port in slave mode with an OLRCK input that is asynchronous to the
incoming AES3 data, the interrupt bit OSLIP (bit 5 in the Interrupt 1 Status register, 0Dh) is provided to in-
dicate when repeated or dropped samples occur. Refer to Figure 8 for the AES3 data format diagram.
When the serial output port is configured as slave, depending on the relative frequency of OLRCK to the
input AES3 data (Z/X) preamble frequency, the data will be slipped or repeated at the output of the CS8416.
After a fixed delay from the Z/X preamble (a few periods of the internal clock, which is running at 256Fs),
the circuit will look back in time until the previous Z/X preamble and check which of the following conditions
occurred:
1. If during that time, the internal data buffer was not updated, a slip has occurred. Data from the previous
frame will be output and OSLIP will be set to 1. Due to the OSLIP bit being “sticky,” it will remain 1 until
the register is read. It will then be reset until another slip/repeat condition occurs.
2. If during that time the internal data buffer did not update between two positive or negative edges (de-
pending on OLRPOL) of OLRCK, a repeat has occurred. In this case, the buffer data was updated twice,
so the part has lost one frame of data. This event will also trigger OSLIP to be set to 1. Due to the OSLIP
bit being “sticky,” it will remain 1 until the register is read. It will then be reset until another slip/repeat
condition occurs.
3. If during that time, it did see a positive edge on OLRCK (or negative edge if the SOLRPOL is set to 1)
no slip or repeat has happened. Due to the OSLIP bit being “sticky,” it will remain in its previous state
until either the register is read or a slip/repeat condition occurs.
If the user reads OSLIP as soon as the event triggers, over a long period of time the rate of occurring INT
will be equal to the difference in frequency between the input AES data and the slave serial output LRCK.
The CS8416 uses a hysteresis window when a slip/repeat event occurs. The slip/repeat is triggered when
an edge of OLRCK passes a window size from the beginning of the Z/X preamble. Without the hysteresis
window, jitter on OLRCK with a frequency very close to Fs could slip back and forth, causing multiple slip/re-
peat events. The CS8416 uses a hysteresis window to ensure that only one slip/repeat happens even with
jitter on OLRCK
Figure 8. AES3 Data Format
X
Channel A
Data
Y
Channel B
Data
Z
Y
X
Y
Channel A
Data
Channel B
Data
Channel A
Data
Channel B
Data
Frame 191
Frame 0
Frame 1
Preambles
OLRCK (in slave mode)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CS8416-DZZR 功能描述:音頻發(fā)送器、接收器、收發(fā)器 IC 192 kHz Digital Audio Receiver RoHS:否 制造商:Cirrus Logic 工作電源電壓:3.3 V, 5 V 電源電流:11.8 mA 通道數(shù)量:1 最大工作溫度:+ 70 C 接口類(lèi)型:I2C, SPI 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSSOP-28 封裝:
CS8416-IS 制造商:CIRRUS 制造商全稱(chēng):Cirrus Logic 功能描述:192 kHZ DIGITAL AUDIO INTERFACE RECEIVER
CS8416-IZ 制造商:CIRRUS 制造商全稱(chēng):Cirrus Logic 功能描述:192 kHZ DIGITAL AUDIO INTERFACE RECEIVER
CS841A1 制造商:HVPSI 制造商全稱(chēng):High Voltage Power Solutions, Inc. 功能描述:MOV Modules
CS841A2 制造商:HVPSI 制造商全稱(chēng):High Voltage Power Solutions, Inc. 功能描述:MOV Modules
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