參數(shù)資料
型號: CS8406-DZZ
廠商: Cirrus Logic Inc
文件頁數(shù): 8/28頁
文件大小: 0K
描述: IC XMITTER DGTL 192KHZ 28TSSOP
標準包裝: 50
類型: 數(shù)字音頻接口發(fā)射器
應用: 車載音頻
安裝類型: 表面貼裝
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 28-TSSOP
包裝: 管件
產品目錄頁面: 759 (CN2011-ZH PDF)
配用: 598-1017-ND - BOARD EVAL FOR CS8416 RCVR
其它名稱: 598-1722
16
DS580F6
CS8406
6. CONTROL PORT DESCRIPTION
The control port is used to access the registers, allowing the CS8406 to be configured for the desired operational
modes and formats. The operation of the control port may be completely asynchronous with respect to the audio
sample rates. However, to avoid potential interference problems, the control port pins should remain static if no op-
eration is required.
The control port has two modes: SPI and IC, with the CS8406 acting as a slave device. SPI Mode is selected if
there is a high to low transition on the AD0/CS pin, after the RST pin has been brought high. IC Mode is selected
by connecting the AD0/CS pin through a resistor to VL or GND, thereby permanently selecting the desired AD0 bit
address state.
6.1
SPI Mode
In SPI Mode, CS is the CS8406 chip select signal, CCLK is the control port bit clock (input into the CS8406
from the microcontroller), CDIN is the input data line from the microcontroller, and CDOUT is the output data
line to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling edge.
Figure 10 shows the operation of the control port in SPI Mode. To write to a register, bring CS low. The first
seven bits on CDIN form the chip address and must be 0010000. The eighth bit is a read/write indicator
(R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP), which is
set to the address of the register that is to be updated. The next eight bits are the data which will be placed
into the register designated by the MAP. During writes, the CDOUT output stays in the Hi-Z state. It may be
externally pulled high or low with a 47 k resistor, if desired.
To read a register, the MAP has to be set to the correct address by executing a partial write cycle which
finishes (CS high) immediately after the MAP byte. To begin a read, bring CS low, send out the chip address
and set the read/write bit (R/W) high. The next falling edge of CCLK willclock out the MSB of the addressed
register (CDOUT will leave the high impedance state). The MAP automatically increments so data for suc-
cessive registers will appear consecutively.
MA P
MSB
LSB
DATA
by te 1
by te n
R/W
AD D R ESS
CH IP
ADDRESS
CH IP
CD IN
CC L K
CS
CD OU T
MSB
LSB MSB
LSB
0010000
MAP = Memory Address Pointer, 7 bits, MSB first
High Impedance
Figure 10. Control Port Timing in SPI Mode
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