- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1991 > CS5528-ASZR (Cirrus Logic Inc)IC ADC 24BIT 8CH 24-SSOP PDF資料下載
參數(shù)資料
| 型號： | CS5528-ASZR |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 28/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT 8CH 24-SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 14.8mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個單端，單極；8 個單端，雙極 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁當(dāng)前第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁
CS5521/22/23/24/28
34
DS317F8
The variables are defined below.
V0
=
First calibration voltage
V1
=
Second calibration voltage (greater than V0)
Ru
=
Result of any uncalibrated conversion
Ru0
=
Result of uncalibrated conversion V0
(24-bit integer or 2’s complement)
Ru1
=
Result of uncalibrated conversion of V1
(24-bit integer or 2’s complement)
Rc
=
Result of any conversion
Rc0
=
Desired calibrated result of converting V0
(24-bit integer or 2’s complement)
Rc1
=
Desired calibrated result of converting V1
(24-bit integer or 2’s complement)
Co
=
Offset calibration register value
(24-bit 2’s complement)
Cg
=
Gain calibration register value
(24-bit integer)
1.3.3 Calibration Tips
Calibration steps are performed at the output word
rate selected by the WR2-WR0 bits of the configu-
ration register. Since higher word rates result in
conversion words with more peak-to-peak noise,
calibration should be performed at lower output
word rates.
Also, to minimize digital noise near
the device, the user should wait for each calibration
step to be completed before reading or writing to
the serial port.
For maximum accuracy, calibrations should be per-
formed for offset and gain (selected by changing
the G2-G0 bits of the desired Setup). Note that only
one gain range can be calibrated per physical chan-
nel. If factory calibration of the user’s system is
performed using the system calibration capabilities
of the CS5521/22/23/24/28, the offset and gain reg-
ister contents can be read by the system microcon-
troller and recorded in EEPROM. These same
calibration words can then be uploaded into the off-
set and gain registers of the converter when power
is first applied to the system, or when the gain range
is changed.
1.3.4 Limitations in Calibration Range
System calibration can be limited by signal head-
room in the analog signal path inside the chip as
discussed under the Analog Input section of this
data sheet. For gain calibration the full-scale input
signal can be reduced to the point in which the gain
register reaches its upper limit of (4-2-22 decimal)
or FFFFFF (hexadecimal). Under nominal condi-
tions, this occurs with a full-scale input signal
equal to about 1/4 the nominal full scale. With the
converter’s intrinsic gain error, this full-scale input
signal may be higher or lower. In defining the min-
imum Full Scale Calibration Range (FSCR) under
ANALOG CHARACTERISTICS, margin is retained
to accommodate the intrinsic gain error. Alterna-
tively the input full-scale signal can be increased to
a point in which the modulator reaches its 1’s den-
sity limit of 80 percent, which under nominal con-
dition occurs when the full-scale input signal is 1.5
times the nominal full scale. With the chip’s intrin-
sic gain error, this full-scale input signal may be
higher or lower. In defining the maximum FSCR,
margin is again incorporated to accommodate the
intrinsic gain error. In addition, for full-scale inputs
greater than the nominal full-scale value of the
range selected, there is some voltage at which var-
ious internal circuits may saturate due to limited
amplifier headroom. This is most likely to occur in
the 100 mV range.
1.4 Performing Conversions and Reading
the Data Conversion FIFO
The CS5521/22/23/24/28 offers various modes of
performing conversions. The sections that follow
detail the differences between the conversion
modes. The sections also provide examples illus-
trating how to use the conversion modes with the
channel-setup registers and to acquire conversions
for further processing. While reading, note that the
CS5521/22 have a FIFO which is four words deep.
The CS5523/24 have a FIFO which is eight words
deep and the CS5528 has a FIFO which is sixteen
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CS5529-ASZR | IC ADC 16BIT W/6BIT LATCH 20SSOP |
| CS5530-ISZR | IC ADC 24BIT 1CH W/LNA 20-SSOP |
| CS5534-ASZR | IC ADC 24BIT 4CH W/LNA 24-SSOP |
| CS5534-BSZR | IC ADC 24BIT 4CH W/LNA 24SSOP |
| CS5550-ISZR | IC ADC 2CH LOW-COST 24-SSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS5529 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:16 BIT PROGRAMMABLE ADC WITH 6 BIT LATCH |
| CS5529_05 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:16-bit, Programmable ΔΣ ADC with 6-bit Latch |
| CS5529-AP | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Prgrmmbl Delta Sigma ADC w/6-Bit Lat-Ch RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| CS5529AS | 制造商:CIRRUS 功能描述:New |
| CS5529-AS | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Prgrmmbl Delta Sigma ADC w/6-Bit Lat-Ch RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。