參數(shù)資料
型號： CS5528-ASZR
廠商： Cirrus Logic Inc
文件頁數(shù)： 25/56頁
文件大?。?/td> 0K
描述： IC ADC 24BIT 8CH 24-SSOP
標準包裝： 1,000
位數(shù)： 24
數(shù)據(jù)接口： 串行
轉換器數(shù)目： 1
功率耗散（最大）： 14.8mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-SSOP（0.209"，5.30mm 寬）
供應商設備封裝： 24-SSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 8 個單端，單極；8 個單端，雙極
CS5521/22/23/24/28
DS317F8
31
1.3 Calibration
The CS5521/22/23/24/28 offer four different cali-
bration functions including self calibration and sys-
tem calibration. However, after the devices are
reset, the converter is functional and can perform
measurements without being calibrated. In this
case, the converter will utilize the initialized values
of the on-chip registers (Gain = 1.0, Offset = 0.0)
to calculate output words for the
±100 mV range.
Any initial offset and gain errors in the internal cir-
cuitry of the chip will remain.
The gain and offset registers, which are used for
both self and system calibration, are used to set the
zero and full-scale points of the converter’s transfer
function. One LSB in the offset register is 2-24 pro-
portion of the input span when the gain register is
set to 1.0 decimal (bipolar span is 2 times the uni-
polar span). The MSB in the offset register deter-
mines if the offset to be trimmed is positive or
negative (0 positive, 1 negative). The converter can
typically trim ±50 percent of the input span. The
gain register spans from 0 to (4 - 2-22). The decimal
equivalent meaning of the gain register is:
where the binary numbers have a value of either
zero or one (b0 corresponds to bit MSB-1, N=22).
Refer to Table 5 for details.
The offset and gain calibration steps each take one
conversion cycle to complete. At the end of the cal-
ibration step, SDO falls to indicate that the calibra-
tion has finished.
1.3.1 Self Calibration
The CS5521/22/23/24/28 offer both self-offset and
self-gain calibrations. For self calibration of offset
in the 25 mV, 55 mV, and 100 mv ranges, the con-
verters internally tie the inputs of the instrumenta-
tion amplifier together and route them to the AIN-
pin as shown in Figure 11 (in the CS5528 they are
routed to AGND). For proper self-calibration of
Table 5. Offset and Gain Registers
Offset Register
One LSB represents 2-24 proportion of the input span when gain register is set to 1.0 decimal (bipolar span is
2 times unipolar span)
Offset and data word bits align by MSB (bit MSB-4 of offset register changes bit MSB-4 of data)
Gain Register
The gain register span is from 0 to (4-2-22). After Reset the (MSB-1) bit is 1, all other bits are 0.
MSB
LSB
Register
Sign
2-2
2-3
2-4
2-5
2-6
2-19
2-20
2-21
2-22
2-23
2-24
Reset (R)
0
000000
MSB
LSB
Register
21
20
2-1
2-2
2-3
2-4
2-17
2-18
2-19
2-20
2-21
2-22
Reset (R)
0
1
0
000000
≈
Db
MSB
2
1
b
(
0
2
0
b
1
2
1
–
… b
N
2
N
– )
++
+
b
MSB
2
1
b
i
2
i
–
i
0
=
N
+
==
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