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參數(shù)資料
| 型號： | CS5523-ASZR |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 29/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 4CH 24-SSOP |
| 標準包裝： | 1,000 |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 10mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個差分，單極；4 個差分，雙極 |
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CS5521/22/23/24/28
DS317F8
35
conversion words deep. Further note that the type
of conversion(s) performed and the way to access
the resulting data from the FIFO is determined by
the MC (multiple conversion), the LP (loop), the
RC (read convert), and the DP (depth pointer) bits
in the configuration register.
1.4.1 Conversion Protocol
The CS552x offer six different conversion modes,
which can be categorized into two main types of
conversions: one-Setup conversions, which refer-
ence only one Setup, and multiple-Setup conver-
sions, which reference any number of Setups. The
converter can be instructed to perform single con-
versions or repeated conversions (with or without
wait) in either of these modes, using the MC, LP,
and RC bits in the Configuration Register. The MC
bit controls whether the part will do one-Setup or
multiple-Setup conversions. The LP bit controls
whether the part will perform a single or repeated
conversion set. When doing repeated conversion
sets, the RC bit controls whether or not the convert-
er will wait for the data from the current conversion
set to be read before beginning the next conversion
set. The sections that follow further detail the vari-
ous conversion modes.
1.4.1.1 Single, One-Setup Conversion
(LP = 0 MC = 0 RC = X)
In this conversion mode, the ADC will perform a
single conversion, referencing only one Setup, and
return to command mode after the data word has
been fully read. The 8-bit command word contains
the CSRP bits, which instruct the converter which
Setup to use when performing the conversion.
To perform a single, one-Setup conversion, the MC
and LP bits in the Configuration Register must be
set to '0'. Then, the 8-bit command word that refer-
ences the desired Setup must be sent to the convert-
er. The ADC will then perform a single conversion
on the referenced Setup, and SDO will fall to indi-
cate that the conversion is complete. Thirty-two
SCLKs are then needed to read the conversion
word from the data register. The first 8 SCLKs are
used to clear the SDO flag. During the last 24
SCLKs, the data word will be output from the con-
verter on the SDO line. The part returns to com-
mand mode immediately after the data word has
been read, where it waits for the next command to
be issued.
1.4.1.2 Repeated One-Setup Conversions with-
out Wait
(LP = 1 MC = 0 RC = 0)
In this conversion mode, the ADC will repeatedly
perform conversions, referencing only one Setup.
The 8-bit command word contains the CSRP bits,
which instruct the converter which Setup to use
when performing the conversion. Note that in this
mode, the part will continually perform conver-
sions, and the user need not read every conversion
as it becomes available. Although conversions can
be read whenever they are needed, they must be
read within one conversion cycle (defined by the
referenced Setup), as the data word will be over-
written when new conversion data becomes avail-
able. The SDO line rises and falls to indicate the
availability of new conversion data. When new
data is available, the current conversion data will
be lost, or in the case that the user has only read a
part of the conversion word, the remainder of the
conversion word will be corrupted.
To perform repeated, one-Setup conversions with
no wait, the MC bit must be set to '0', the LP bit
must be set to '1', and the RC bit must be set to '0'
in the Configuration Register. Then, the 8-bit com-
mand word that references the desired Setup must
be sent to the converter. The ADC will then begin
performing conversions on the referenced Setup,
and SDO will fall to indicate when a conversion is
complete, and data is available. Thirty-two SCLKs
are then needed to read the conversion word from
the data register. The first 8 SCLKs are used to
clear the SDO flag. During the last 24 SCLKs, the
data word will be output from the converter on the
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| CS5524-ASZ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 4-Ch 24-Bit Delta Sigma ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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