1.2.6.1 Latch Outputs The A1-A0 pins mimic the latch output, D23/D11- D22/D10, bits of the channel-setup register" />
參數(shù)資料
型號(hào)： CS5523-ASZR
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 21/56頁(yè)
文件大小： 0K
描述： IC ADC 16BIT 4CH 24-SSOP
標(biāo)準(zhǔn)包裝： 1,000
位數(shù)： 16
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 10mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 24-SSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 4 個(gè)差分，單極；4 個(gè)差分，雙極
CS5521/22/23/24/28
28
DS317F8
1.2.6.1 Latch Outputs
The A1-A0 pins mimic the latch output, D23/D11-
D22/D10, bits of the channel-setup registers. A1-A0
can be used to control external multiplexers and oth-
er logic functions outside the converter. The outputs
can sink or source at least 1 mA, but it is recom-
mended to limit drive currents to less than 20
μA to
reduce self-heating of the chip. These outputs are
powered from VA+, hence their output voltage for
a logic 1 will be limited to the VA+ supply voltage.
1.2.6.2 Channel Select Bits
The channel select, CS1-CS0, bits are used to de-
termine which physical input channel will be used
when a conversion is performed with a particular
Setup.
1.2.6.3 Output Word Rate Selection
The word rate, WR2-WR0, bits of the channel-set-
up registers set the output conversion word rate of
the converter when a conversion is performed with
a particular Setup. The word rates indicated in
Table 3 assume a master clock of 32.768 kHz, and
scale linearly when using other master clock fre-
quencies. Upon reset the converter is set to operate
with an output word rate of 15.0 Sps.
1.2.6.4 Gain Bits
The gain bits, G2-G0, of the channel-setup regis-
ters set the full-scale differential input range for the
ADC when a conversion is performed with a partic-
ular Setup. The input ranges in the table assume a
2.5 V reference voltage, and scale linearly when
using other reference voltages.
1.2.6.5 Unipolar/Bipolar Bit
The unipolar/bipolar bit is used to determine the
type of conversion, unipolar or bipolar, that will be
performed with a particular Setup.
1.2.7 Configuration Register
The configuration register is 24 bits long. The fol-
lowing subsections detail the bits in the configura-
tion register. Table 4 summarizes the configuration
register.
1.2.7.1 Chop Frequency Select
The chop frequency select (CFS1-CFS0) bits are
used to set the rate at which the instrumentation
amplifier’s chop switches modulate the input sig-
nal. The 256 Hz rate is desirable as it provides the
lowest input CVF (sampling) current, <300 pA
over -40 to 85
°C. The higher rates can be used to
eliminate modulation/aliasing effects as the fre-
quency of the input signal increases.
1.2.7.2 Conversion/Calibration Control Bits
The conversion/calibration control bits in the con-
figuration register are used to control the particular
type of conversion required for the users applica-
tions. In short, the depth pointer (DP3-DP0) bits
determine the number of Setups that will be refer-
enced when conversions are performed. The multi-
ple conversion (MC) bit instructs the converter to
perform conversions on the number of Setups in the
channel-setup registers which are referenced by the
depth pointer bits. The converter begins with
Setup1 and moves sequentially through the Setups
in this mode. The Loop (LP) bit instructs the con-
verter to continuously perform conversions until a
Stop command is sent to the converter. The read
convert (RC) bit instructs the converter to wait until
the conversion data is read before performing the
next conversion or set of conversions.
1.2.7.3 Power Consumption Control Bits
The CS5522/24/28 devices provide three power
consumption modes: normal, low power,
and
sleep. The CS5521/23 provide two power con-
sumption modes: normal, and sleep. The normal
(default) mode is entered after a power-on reset. In
normal mode, the CS5522/24/28 typically con-
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