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參數(shù)資料
| 型號(hào)： | CS5373A-ISZR |
| 廠商： | Cirrus Logic Inc |
| 文件頁(yè)數(shù)： | 24/40頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC/MODULATOR LP/HP 28-SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類(lèi)型： | 調(diào)制器 |
| 分辨率（位）： | 24 b |
| 采樣率（每秒）： | 512k |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 電源電壓： | ± 2.5V，3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 帶卷 (TR) |
| 配用： | CDB5378-ND - EVALUATION BOARD FOR CS5378 |
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CS5373A
30
DS703F2
tests and two external differential inputs. One
external input is typically dedicated to sensor
measurements and the other to testing the
electronics channel.
The OUT± outputs are enabled in all opera-
tional
modes
except
modulator
mode
(MODE 0), “AC BUF Only” mode (MODE 3)
and sleep mode (MODE 7). In modulator
mode, AC BUF Only mode and sleep mode
the OUT± pins are high impedance.
7.4 DAC BUF± Buffered Output
The test DAC BUF± pins are buffered differen-
tial analog outputs for testing external sensors
such as geophones or hydrophones. The buff-
ered outputs have reduced performance spec-
ifications compared with the OUT± outputs,
but are less sensitive to external loading.
The BUF± outputs are enabled in all operation-
al modes except modulator mode (MODE 0),
“AC OUT Only” mode (MODE 2) and sleep
mode
(MODE 7).
In
modulator
mode,
AC OUT only and sleep mode the BUF± pins
are high impedance to ensure they do not in-
terfere with sensor operation during normal
data acquisition.
For sensor impedance testing, it is required to
place matched series resistors in between the
BUF± outputs and the differential sensor. With
known series resistors and a known DC differ-
ential source voltage, sensor resistance can
be calculated ratiometrically from the mea-
sured voltage drop across the sensor.
7.5 DAC CAP± Connection
The CS5373A test DAC requires a 10 nF C0G
type capacitor to be connected differentially
across the CAP± pins. This capacitor creates
an internal anti-alias filter to eliminate high-fre-
quency signals from the OUT± and BUF± ana-
log outputs and helps to maintain the stability
of the low-power
ΔΣ DAC circuitry.
A COG, NPO or similar high-quality capacitor
is required for CAP
± since other capacitor
types, such as X7R, do not have the required
linearity. Using a poor-quality capacitor on
CAP± will significantly degrade THD perfor-
mance of the test DAC AC operational modes.
7.6 Analog Differential Signals
Differential AC test signals into and out of the
CS5373A consist of two halves with equal but
opposite magnitude varying about a common
mode voltage. A full-scale 5 VPP differential
AC signal centered on a -0.15 V common
mode voltage will have:
SIG+ = -0.15 V + 1.25 V = +1.1 V
SIG- = -0.15 V - 1.25 V = -1.4 V
SIG+ is +2.5 V relative to SIG-
For the opposite case:
SIG+ = -0.15 V - 1.25 V = -1.4 V
SIG- = -0.15 V + 1.25 V = +1.1 V
SIG+ is -2.5 V relative to SIG-
So the total swing for SIG+ relative to SIG- is
(+2.5 V) - (-2.5 V) = 5 Vpp differential. A similar
calculation can be done for SIG- relative to
SIG+. It’s important to note that a 5 Vpp differ-
ential signal centered on a -0.15 V common
mode voltage never exceeds +1.1 V with re-
spect to ground and never drops below -1.4 V
with respect to ground on either half. By defini-
tion, differential voltages are measured with
respect to the opposite half, not relative to
ground. A voltmeter differentially measuring
between SIG+ and SIG- in the above example
would correctly read 1.767 Vrms, or 5 Vpp.
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