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參數(shù)資料
| 型號： | CS5372A-ISZR |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 13/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MODULATOR LP/HP 2CH 24-SSOP |
| 標準包裝： | 1,000 |
| 類型： | 調(diào)制器 |
| 分辨率（位）： | 24 b |
| 采樣率（每秒）： | 512k |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 電源電壓： | ±2.5V，3.3 V ~ 5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SSOP（0.209"，5.30mm 寬） |
| 供應商設備封裝： | 24-SSOP |
| 包裝： | 帶卷 (TR) |
| 配用： | 598-1778-ND - EVALUATION BOARD FOR CS5376 |
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CS5371A CS5372A
20
DS748F3
6. POWER MODES
The CS5371A and CS5372A modulators have
three power modes. Normal operation, power
down with MCLK enabled, and power down
with MCLK disabled.
6.1 Normal Operation
With MCLK active and the PWDN pin driven
low, the CS5371A and CS5372A modulators
perform normal data acquisition. A differential
analog input signal is converted to an overs-
ampled 1-bit
ΔΣ bit stream at 512 kHz. This ΔΣ
bit stream is then digitally filtered and decimat-
ed by the CS5376A device to a high-precision
24-bit output.
6.2 Power Down, MCLK Enabled
With MCLK active and the PWDN pin driven
high, the CS5371A and CS5372A modulators
are placed into a power-down state. During
this power-down state the modulators are dis-
abled and all outputs are high impedance.
6.3 Power Down, MCLK Disabled
If MCLK is stopped, an internal loss-of-clock
detection circuit automatically places the
CS5371A and CS5372A into a power-down
state. This power-down state is independent of
the PWDN pin setting and is automatically in-
voked after approximately 40
μs without re-
ceiving an incoming MCLK edge.
During this power-down state, the modulators
are disabled and all outputs are high imped-
ance. When used with the CS5376A digital fil-
ter, the CS5371A and CS5372A are in this
power-down state immediately after reset
since MCLK is disabled by default.
NORMAL OPERATION
MCLK = ON
PWDN = 0
POWER DOWN
MCLK = ON
PWDN = 1
POWER DOWN
MCLK = OFF
PWDN = X
Figure 13. Power Mode Diagram
相關PDF資料 |
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| M83723/78R10056 | CONN PLUG 5POS STRAIGHT W/PINS |
| CS5371A-ISZ | IC MODULATOR LP/HP 1CH 24-SSOP |
| M83723/72A16246 | CONN RCPT 24POS WALL MT W/PINS |
| MS27484T16A6P | CONN PLUG 6POS STRAIGHT W/PINS |
| CS5371A-ISZR | IC MODULATOR LP/HP 1CH 24-SSOP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CS5372-BS | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC LP High Performance Delta Sigma Mod. RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| CS5372-BSR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC LP High Performance Delta Sigma Mod. RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| CS5372-BSZ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC IC LP Hgh Prfrmnc Delta Sigma Modultr RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| CS5372-BSZR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC LP High Performance Delta Sigma Mod. RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| CS5373A | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low-power, High-performance Modulator and Test DAC |
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