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| 型號： | CS5303GDW28 |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁數(shù)： | 13/20頁 |
| 文件大?。?/td> | 176K |
| 代理商： | CS5303GDW28 |
CS5303
http://onsemi.com
13
order to reduce voltage excursions during transients.
Adaptive voltage positioning can reduce peak–peak output
voltage deviations during load transients and allow for a
smaller output filter. The output voltage can be set higher at
light loads to reduce output voltage sag when the load
current is stepped up and set lower during heavy loads to
reduce overshoot when the load current is stepped up. For
low current applications a droop resistor can provide fast
accurate adaptive positioning. However at high currents, the
loss in a droop resistor becomes excessive. For example; in
a 50 A converter a 1 m
resistor to provide a 50 mV change
in output voltage between no load and full load would
dissipate 2.5 Watts.
Lossless adaptive positioning is an alternative to using a
droop resistor, but must respond quickly to changes in load
current. Figure 14 shows how adaptive positioning works.
The waveform labeled normal shows a converter without
adaptive positioning. On the left, the output voltage sags
when the output current is stepped up and later overshoots
when current is stepped back down. With fast (ideal)
adaptive positioning the peak to peak excursions are cut in
half. In the slow adaptive positioning waveform the output
voltage is not repositioned quickly enough after current is
stepped up and the upper limit is exceeded.
Adaptive Positioning
Limits
Adaptive Positioning
Normal
Fast
Slow
Figure 14. Adaptive Positioning
The CS5303 uses two methods to provide fast and
accurate adaptive positioning. For low frequency
positioning the V
FB
and V
DRP
pins are used to adjust the
output voltage with varying load currents. For high
frequency positioning, the current sense input pins can be
used to control the power stage output impedance. The
transition between fast and slow positioning is adjusted by
the error amp compensation.
The CS5303 can be configured to adjust the output
voltage based on the output current of the converter. The
adaptive positioning circuit is designed to select the DAC
setting as the maximum output voltage. (Refer to
Application Diagram on page 2.)
To set the no–load positioning a resistor (R9) is placed
between the output voltage and V
FB
pin. The V
FB
bias
current will develop a voltage across the resistor to decrease
the output voltage. The V
FB
bias current is dependent on the
value of ROSC. See Figure 4 on the datasheet.
During no load conditions the V
DRP
pin is at the same
voltage as the V
FB
pin, so none of the V
FB
bias current flows
through the V
DRP
resistor (R8). When output current
increases the V
DRP
pin increases proportionally and the
V
DRP
pin current offsets the V
FB
bias current and causes the
output voltage to further decrease.
The V
FB
and V
DRP
pins take care of the slower and DC
voltage positioning. The first few
μ
s are controlled primarily
by the ESR and ESL of the output filter. The transition
between fast and slow positioning is controlled by the ramp
size and the error amp compensation. If the ramp size is too
large or the error amp too slow there will be a long transition
to the final voltage after a transient. This will be most
apparent with lower capacitance output filters.
Note: Large levels of adaptive positioning can cause pulse
width jitter.
Error Amp Compensation
The transconductance error amplifier can be configured to
provide both a slow soft–start and a fast transient response.
C4 in the main applications diagram controls soft–start. A
0.1
μ
F capacitor with the 30
μ
A error amplifier output
capability will allow the output to ramp up at 0.3 V/ms or
1.5 V in 5 ms.
R10 is connected in series with C4 to allow the error
amplifier to slew quickly over a narrow range during load
transients. Here the 30
μ
A error amplifier output capability
works against 10 k
(R10) to limit the window of fast
slewing too 300 mV – enough to allow for fast transients, but
not enough to interfere with soft–start. This window will be
noticeable as a step in the COMP pin voltage at start–up. The
size of this step must be kept smaller than the Channel
Start–Up Offset (nominally 0.4 V) for proper soft–start
operation. If adaptive positioning is used the R9 and R8 form
a divider with the V
DRP
end held at the DAC voltage during
start–up, which effectively makes the Channel Start–Up
Offset larger.
C12 is included for error amp stability. A capacitive load
is required on the error amp output. Use of values less than
1 nF may result in error amp oscillation of several MHz.
C11 and the parallel resistance of the V
FB
resistor (R9)
and the V
DRP
resistor (R8) are used to roll off the error amp
gain. The gain is rolled off at a high enough frequency to give
a quick transient response, but low enough to cross zero dB
well below the switching frequency to minimize ripple and
noise on the COMP pin.
UVLO
The CS5303 has undervoltage lockout functions
connected to two pins. One intended for the logic and
low–side drivers with a 4.4 V turn–on threshold is
connected to the V
CCLL1
pin. A second for the high side
drivers has a 2 V threshold and is connected to the V
CCH12
pin.
The UVLO threshold for the high side drivers was chosen
at a low value to allow for flexibility in the part and an input
voltage as low as 3.3 V. In many applications this will be
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| CS5303GDWR28 | Analog IC |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS5303GDWR28 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CS5305 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Three−Phase Synchronous Switching Step−Down Controller with Single Wire Current Sharing |
| CS5305/D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Three-Phase Synchronous Switching Step-Down Controller with Single Wire Current Sharing |
| CS5305GDW28 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:ON Semiconductor 功能描述: |
| CS5305GDWR28 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Three−Phase Synchronous Switching Step−Down Controller with Single Wire Current Sharing |
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