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參數(shù)資料
| 型號： | CS4354-CSZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 10/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 24BIT SRL 14SOIC |
| 特色產(chǎn)品： | CS4354 Stereo D/A Converter |
| 標(biāo)準(zhǔn)包裝： | 48 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 65mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-SOIC |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電壓，單極 |
| 采樣率（每秒）： | 192k |
| 產(chǎn)品目錄頁面： | 757 (CN2011-ZH PDF) |
| 其它名稱： | 598-1808 CS4354-CSZ-ND |
18
DS895F2
CS4354
4.9
Recommended Operational Sequences
The following sequences are recommended for minimal pops and clicks when transitioning between differ-
ent states of operation.
4.9.1
Power-Up
1.
Turn on power supplies.
2.
Wait for power supply voltages to stabilize.
3.
Apply the serial port clocks and data.
Provide the correct MCLK, LRCK, and SCLK (only in External Serial Clock Mode); please refer to
Section 4.4 on page 14 for common clock frequencies in the External Serial Clock Mode, and
supported modes in the Internal Serial Clock Mode. The sequence will complete and audio will be
output from the AOUTx pins within 50 ms after valid clocks are applied.
4.9.2
Power-Down
1.
Stop LRCK.
2.
Wait 5 ms.
3.
Stop MCLK without applying any glitched pulses to the MCLK pin.
A glitched pulse is any pulse that is shorter than the period defined by the minimum/maximum MCLK
signal duty cycle specification and the nominal frequency of the input MCLK signal. A transient may
occur on the analog outputs if the MCLK signal duty cycle specification is violated when the MCLK
signal is removed during normal operation; see “Switching Specifications - Serial Audio Interface” on
4.
Turn off power supplies.
4.9.3
Sample Rate Change
1.
Stop LRCK.
2.
Wait 5 ms.
3.
Stop MCLK without applying any glitched pulses to the MCLK pin.
A glitched pulse is any pulse that is shorter than the period defined by the minimum/maximum MCLK
signal duty cycle specification and the nominal frequency of the input MCLK signal. A transient may
occur on the analog outputs if the MCLK signal duty cycle specification is violated when the MCLK
signal is removed during normal operation; see “Switching Specifications - Serial Audio Interface” on
4.
Wait 2 ms.
This wait time is dictated by the discharge time of the recommended 2.2 F FILT+ capacitor (see
“Typical Connection Diagram” on page 12). Higher capacitance values will require longer wait times.
5.
Apply the serial port clocks and data.
Provide the correct MCLK, LRCK, and SCLK (only in External Serial Clock Mode); please refer to
Section 4.4 on page 14 for common clock frequencies in the External Serial Clock Mode, and
supported modes in the Internal Serial Clock Mode. The sequence will complete, and audio will be
output from the AOUTx pins within 50 ms after valid clocks are applied.
4.10
Grounding and Power Supply Arrangements
As with any high-resolution converter, the CS4354 requires careful attention to power supply and grounding
arrangements if its potential performance is to be realized. The “Typical Connection Diagram” on page 12
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS4354-CSZR | 制造商:Cirrus Logic 功能描述:5V DAC W/ 2VRMS LINE DRIVER - Tape and Reel 制造商:Cirrus Logic 功能描述:DAC 制造商:Cirrus Logic 功能描述:IC DAC 24BIT SRL 14SOIC |
| CS4355-CSZ | 制造商:Cirrus Logic 功能描述:5-V STEREO DAC WITH 2-VRMS GROUND-CENTERED OUTPUT - Bulk 制造商:Cirrus Logic 功能描述:DAC |
| CS4355-CSZR | 制造商:Cirrus Logic 功能描述:5-V STEREO DAC WITH 2-VRMS GROUND-CENTERED OUTPUT - Tape and Reel 制造商:Cirrus Logic 功能描述:DAC |
| CS4-36 | 制造商:SUPERWORLD 制造商全稱:Superworld Electronics 功能描述:POWER TRANSFORMER |
| CS4360 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:24-Bit, 192 kHz 6 Channel D/A Converter |
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