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參數(shù)資料
| 型號： | CS4207-DNZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 19/77頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CODEC AUD HDPN AMP AUTO 48QFN |
| 標(biāo)準(zhǔn)包裝： | 429 |
| 類型： | 音頻編解碼器 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 24 b |
| ADC / DAC 數(shù)量： | 2 / 3 |
| 三角積分調(diào)變： | 是 |
| 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： | 105 / 110 |
| 電壓 - 電源，模擬： | 2.97 V ~ 5.25 V |
| 電壓 - 電源，數(shù)字： | 2.97 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-QFN |
| 供應(yīng)商設(shè)備封裝： | 48-QFN-EP（6x6） |
| 包裝： | 托盤 |
| 其它名稱： | 598-1798 |
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26
DS880F4
CS4207
If RESET# is asserted low, and BITCLK and SYNC are not running at the time (defined as link low power
state), the codec will signal the power state change request and initialization request asynchronously by as-
serting SDI high continuously until it detects the de-assertion of RESET#. It will then asynchronously drive
SDI low with the de-assertion of the RESET#. With the RESET# signal high, the codec will reestablish the
connection with the controller by performing a “Codec Initialization request”.
4.4
D3 Lower Power State Support
The
D3 low power state allows for, but does not require, the lowest possible power consuming state under
software control, in which Extended Power States Supported
(EPSS) requirements can be met. While in
the D3 state, the CS4207 will retain sufficient operational capability to properly respond to subsequent soft-
ware Get/Set Power State commands (Verb ID=F05h/705h) to the Audio Function Group (Node ID = 01h).
In addition, while in the D3 power state, Link Reset and “Double Function Group” reset are supported. All
other Get/Set commands will be ignored while the codec is in the D3 power state.
Widgets reporting an EPSS of ‘1’b will transition from D3 state to D0 state in less than 10 ms. This interval
is measured from the response to the Set Power State verb that caused the transition from D3 back to fully
operational D0 state.
It is permissible for the audio fidelity for analog outputs to be slightly degraded if audio playback begins im-
mediately once the fully operational state is entered. However, audio fidelity will not be degraded 75ms after
the transitioning to D0 state.
4.5
Extended Power States Supported (EPSS)
EPSS indicates that the Audio Function Group or a particular Widget supports additional capabilities allow-
ing better low power operation. The CS4207 will report EPSS support at the Function group level and will
enable low power operation for all Input and Output Converter Widgets, and the following pin widgets which
are capable of reporting presence detection:
–
Headphone pin widget (node ID 09h)
–
Line Out 1 pin widget (node ID 0Ah)
–
Line In 1/Mic In 2 pin widget (node ID 0Ch)
–
Mic In 1/Line In 2 pin widget (node ID 0Dh)
–
S/PDIF Receiver Input pin widget (node ID 0Fh).
The following requirements will also be implemented by each input/output converter widget and the above
listed pin widgets:
Report PowerCntrl set to ‘1’b and support the Supported Power States verb.
Jack Presence state change reporting (when enabled) will operate regardless of the Widget and Audio
Function Group power state.
Reporting of presence state change and issuing system wake when the link clock (BITCLK) is not oper-
ational is supported.
The S/PDIF Receiver to S/PDIF Transmitter digital loop-through (no clock re-timing) will continue to op-
erate (if enabled) even though any one, or all of the S/PDIF Receiver Input Converter Widget, S/PDIF
Transmitter Output Converter Widget or S/PDIF Receiver Input Pin Widget enters into low power states.
This digital loop-through will also continue to operate if the Audio Function Group is placed in the D3 low
power state, during a Link Reset, and even if the HD Audio BITCLK is stopped.
Dependencies between converter widgets and associated pin widgets will not cause unexpected results
when one node of the dependency is placed into D3 state. The diagrams and tables below demonstrate
typical audio streams.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS4207-DNZR | 功能描述:接口—CODEC IC Lo Pwr,4/6 HD Aud Codec w/HP Amp RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| CS42080DR8 | 制造商:ON Semiconductor 功能描述: |
| CS4210 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:IEEE 1394 OHCI Controller |
| CS4210A-CNZ | 制造商:Cirrus Logic 功能描述:IC LOW POWER HD AUDIO CODEC - Bulk 制造商:Cirrus Logic 功能描述:HD CODEC |
| CS4210A-CNZR | 功能描述:IC LOW POWER HD AUDIO CODEC RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:* 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
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