參數(shù)資料
型號(hào)： CP2200-GQ
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 35/108頁(yè)
文件大小： 0K
描述： IC ETH CTRLR SNGL-CHIP 48TQFP
標(biāo)準(zhǔn)包裝： 250
控制器類型： 以太網(wǎng)控制器，MAC/10Base-T
接口： 并行/串行
電源電壓： 3.1 V ~ 3.6 V
電流 - 電源： 75mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 627 (CN2011-ZH PDF)
配用： 336-1316-ND - KIT EVAL FOR CP2201 ETH CTRLR
其它名稱： 336-1312
CP2200/1
32
Rev. 1.0
Register 6. INT0RD: Interrupt Status Register 0 (Read-Only)
Note: Reading this register will not clear INT0 interrupt flags.
Bit 7:
EOPINTR: End of Packet Read-Only Interrupt Flag
0: The last byte of a packet has not been read since the last time EOPIF was cleared.
1: The last byte of a packet has been read.
Bit 6:
RXEINTR: Receive FIFO Empty Read-Only Interrupt Flag
0: The receive FIFO has not been empty since the last time RXFIFOE was cleared.
1: The receive FIFO is empty.
Bit 5:
SELFINTR: Self Initialization Complete Read-Only Interrupt Flag
0: Self Initialization has not completed since the last time SELFINT was cleared.
1: Self Initialization has completed.
Bit 4:
OSCINTR: Oscillator Initialization Complete Read-Only Interrupt Flag
0: Oscillator Initialization has not completed since the last time OSCINT was cleared.
1: Oscillator Initialization has completed.
Bit 3:
FLWEINTR: Flash Write/Erase Operation Complete Read-Only Interrupt Flag
0: A Flash write or erase operation has not completed since the last time FLWEINT was cleared.
1: A Flash write or erase operation has completed.
Bit 2:
TXINTR: Packet Transmitted Read-Only Interrupt Flag
0: A packet transmission has not completed since the last time TXINT was cleared.
1: A packet has been transmitted.
Bit 1:
RXFINTR: Receive FIFO Full Read-Only Interrupt Flag
0: The receive FIFO has not been full since the last time RXFINT was cleared.
1: The receive FIFO is full.
Bit 0:
RXINTR: Packet Received Read-Only Interrupt Flag
0: A packet has not been added to the receive buffer since the last time RXINT was cleared.
1: A packet has been added to the receive buffer.
R
RRR
R
Reset Value
EOPINTR RXEINTR SELFINTR OSCINTR FLWEINTR TXINTR
RXFINTR
RXINTR
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x76
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