參數(shù)資料
型號: CP2112-F02-GM
廠商: Silicon Laboratories Inc
文件頁數(shù): 6/22頁
文件大?。?/td> 0K
描述: IC HID USB-TO-SMBUS BRIDGE
標準包裝: 75
應用: USB 至 SMBus 電橋
接口: SMBus,USB
電源電壓: 1.8V,3 V ~ 3.6 V
封裝/外殼: 24-WFQFN 裸露焊盤
供應商設備封裝: 24-QFN(4x4)
包裝: 管件
安裝類型: 表面貼裝
其它名稱: 336-2149-5
CP2112
14
Rev. 1.2
6.2. SMBus Operation
The CP2112 supports reads, writes, and addressed reads. The master device initiates all three types of data
transfers and provides the clock pulses on SCL. The SMBus interface on the CP2112 operates as a master, but
also has a configurable slave address associated with it that the CP2112 will only ACK upon receiving. Multiple
master devices on the same bus are supported. If two or more masters attempt to initiate a data transfer
simultaneously, an arbitration scheme is employed with a single master always winning the arbitration. Note that it
is not necessary to specify one device as the Master in a system; any device that transmits a START and a slave
address becomes the master for the duration of that transfer.
A typical SMBus transaction consists of a START condition followed by an address byte (Bits7–1: 7-bit slave
address; Bit0: R/W direction bit), one or more bytes of data, and a STOP condition. Bytes that are received (by a
master or slave) are acknowledged (ACK) with a low SDA during a high SCL (see Figures 6, 7, and 8). If the
receiving device does not ACK, the transmitting device will read a NACK (not acknowledge), which is a high SDA
during a high SCL.
The direction bit (R/W) occupies the least-significant bit position of the address byte. The direction bit is set to logic
1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation. All transactions are
initiated by a master, with one or more addressed slave devices as the target. The master generates the START
condition and then transmits the slave address and direction bit. If the transaction is a WRITE operation from the
master to the slave, the master transmits the data one byte at a time waiting for an ACK from the slave at the end
of each byte. For READ operations, the slave transmits the data waiting for an ACK from the master at the end of
each byte. At the end of the data transfer, the master generates a STOP condition to terminate the transaction and
free the bus. Figure 6 illustrates a typical CP2112 read transaction, and Figure 7 illustrates a typical CP2112 write
transaction.
Figure 6. Typical CP2112 Read
Figure 7. Typical CP2112 Write
The CP2112 performs addressed reads using a repeated start. Addressed Reads are implemented by issuing a
START condition followed by a slave address write and logical address. Next the CP2112 issues a repeated
START followed by a slave address read. After this sequence, the CP2112 reads bytes from the slave device. The
CP2112 supports addressed reads on slave devices with up to a 16 byte logical address field. Figure 8 illustrates a
typical addressed read transaction (with a one byte logical address field).
SLA6
SDA
SLA5-0
Read (1)
D7
D6-0
Slave Address + Read
Data Byte
START
ACK
NACK
STOP
SCL
SLA6
SDA
SLA5-0
Write (0)
D7
D6-0
SCL
Slave Address + Write
Data Byte
START
ACK
STOP
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