參數(shù)資料
型號： CMOD232+
廠商： Maxim Integrated Products
文件頁數(shù)： 4/36頁
文件大?。?/td> 0K
描述： EVAL SYSTEM FOR MAX9850
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
系列： *
MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
12
______________________________________________________________________________________
Pin Description
PIN
NAME
FUNCTION
1
LRCLK
Digital Audio Left-Right Clock Input/Output. LRCLK is the audio sample rate clock and determines
whether the audio data on SDIN is routed to the left or right channel. LRCLK is an input when the
MAX9850 is in slave mode and an output when in master mode.
2
BCLK
Digital Audio Bit Clock Input/Output. BCLK is an input when the MAX9850 is in slave mode and an
output when in master mode.
3
SDIN
Digital Audio Serial Data Input
4DVDD
Digital Power-Supply Input. Bypass to DGND with a 1F ceramic capacitor.
5
MCLK
Master Clock Input. All internal digital clocks are derived from MCLK.
6
DGND
Digital Ground
7
ADD
I
2C Address-Select Input. Connect to AGND, AVDD, or SDA to select one of the three possible I2C
addresses.
8
GPIO
General-Purpose Input/Output. Configure GPIO as an input or an output through the GPIO register.
GPIO can perform the function of an interrupt when configured as an output. See the GPIO section.
9
INR
Right-Channel Line Input. INR is mixed with the right DAC output.
10
INL
Left-Channel Line Input. INL is mixed with the left DAC output.
11
OUTR
Line Level Right-Channel Output. OUTR is biased at AGND.
12
OUTL
Line Level Left-Channel Output. OUTL is biased at AGND.
13
REF
Reference Output. Bypass to AGND with a 1F ceramic capacitor.
14
AGND
Analog Ground
15
NREG
Line Output Negative Regulator Output. Bypass to AGND with a 1F capacitor.
16
PREG
Line Output Positive Regulator Output. Bypass to AGND with a 1F capacitor.
17
AVDD
Analog Power Supply. Bypass to AGND with a 1F ceramic capacitor.
18
HPR
Right-Channel Headphone Output. HPR is a DirectDrive output biased at AGND.
19
HPL
Left-Channel Headphone Output. HPL is a DirectDrive output biased at AGND.
20
SVSS
Headphone Amplifier Negative Power-Supply Input. Connect to PVSS.
21
HPS
Headphone Sense Input. Connect to the control pin of a headphone jack for automatic headphone
sensing. Float HPS if unused. See the Headphone Sense Input (HPS) section.
22
PVSS
Inverting Charge-Pump Output. Bypass to PGND with a 2.2F ceramic capacitor and connect to SVSS
to provide the headphone amplifiers with a negative supply.
23
C1N
Charge-Pump Flying Capacitor Negative Terminal. Connect a 0.47F ceramic capacitor between
C1N and C1P.
24
PGND
Charge-Pump Ground
25
C1P
Charge-Pump Flying Capacitor Positive Terminal. Connect a 0.47F ceramic capacitor between C1P
and C1N.
26
PVDD
Charge-Pump and Headphone Amplifier Positive Power-Supply Input. Bypass to PGND with a 1F
ceramic capacitor. Connect to AVDD for normal operation.
27
SCL
I
2C-Compatible Serial Clock Input
28
SDA
I
2C-Compatible Serial Data Input/Output
—
EP
Exposed Thermal Pad. Connect EP to AGND.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CMOD232+ 功能描述:界面開發(fā)工具 Cmod232+ Eval Kit RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
CMOD3003 功能描述:二極管 - 通用，功率，開關(guān) ULTRAMINI SURFACE MOUNT RoHS:否 制造商:STMicroelectronics 產(chǎn)品:Switching Diodes 峰值反向電壓:600 V 正向連續(xù)電流:200 A 最大浪涌電流:800 A 配置: 恢復(fù)時間:2000 ns 正向電壓下降:1.25 V 最大反向漏泄電流:300 uA 最大功率耗散: 工作溫度范圍: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:ISOTOP 封裝:Tube
CMOD3003 BK 制造商:Central Semiconductor Corp 功能描述:Diode Switching 180V 0.6A Box
CMOD3003 TR 制造商:Central Semiconductor Corp 功能描述:Diodes - General Purpose, Power, Switching ULTRAMINI SURFACE MOUNT
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