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參數(shù)資料
| 型號： | CM42-67025V-55 |
| 廠商： | ATMEL CORP |
| 元件分類： | SRAM |
| 英文描述： | 8K X 16 DUAL-PORT SRAM, 55 ns, CQCC84 |
| 封裝： | LCC-84 |
| 文件頁數(shù)： | 7/23頁 |
| 文件大?。?/td> | 257K |
| 代理商： | CM42-67025V-55 |
M 67025
MATRA MHS
Rev. D (29/09/95)
15
AC Electrical Characteristics
over the Full Operating Temperature and Supply Voltage Range
WRITE CYCLE
PARAMETER
M
67025–20
M
67025–25
M
67025–30
M
67025–35
M
67025–45
M
67025–55
UNI
Symbol
(4)
Symbol
(5)
PARAMETER
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
UNI
T
TAVAVW tWC
Write cycle time
20
–
25
–
30
–
35
–
45
–
55
–
ns
TELWH
tSW
Chip select to end of
write (3)
15
–
20
–
25
–
30
40
–
45
–
ns
TAVWH
tAW
Address valid to end
of write
15
–
20
–
25
–
30
40
–
45
–
ns
TAVWL
tAS
Address Set–up Time
0
–
0
–
0
–
0
–
0
–
ns
TWLWH
tWP
Write Pulse Width
15
–
20
–
25
–
30
–
35
–
40
–
ns
TWHAX
tWR
Write Recovery Time
0
–
0
–
0
–
0
–
0
–
0
–
ns
TDVWH
tDW
Data Valid to end of
write
13
–
15
–
20
–
25
–
25
–
30
–
ns
TGHQZ
tHZ
Output high Z time (1,
2)
–
15
–
15
–
15
–
15
–
20
–
25
ns
TWHDX
tDH
Data hold time (4)
0
–
0
–
0
–
0
–
0
–
0
–
ns
TWLQZ
tWZ
Write enable to output
in high Z (1, 2)
–
15
–
15
–
15
–
15
–
20
–
25
ns
TWHQX
tOW
Output active from
end of write (1, 2, 4)
0
–
0
–
0
–
0
–
0
–
0
–
ns
TSWRD
tSWRD
SEM flag write to
read time
10
–
10
–
10
–
10
–
10
–
10
–
ns
TSPS
tSPS
SEM flag contention
window
10
–
10
–
10
–
10
–
10
–
10
–
ns
Notes :
1. Transition is measured
± 500 mV from low or high impedance voltage with load (figures 2 and 3).
2. This parameters is guaranteed but not tested.
3. To access RAM CS = VIL, UB or LB = VIL, SEM = VIH. To access semaphore CS = VIH, SEM = VIL. This condition must be valid
for entire tSW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH
and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW.
5. STD symbol.
6. ALT symbol.
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