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參數(shù)資料
| 型號： | CH7007A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | DIGITAL PC TO TV ENCODER WITH MACROVISION |
| 中文描述： | 電腦數(shù)字電視編碼器和通過Macrovision |
| 文件頁數(shù)： | 7/49頁 |
| 文件大?。?/td> | 278K |
| 代理商： | CH7007A |
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201-0000-002 Rev. 2.7, 08/23/2000
7
CHRONTEL
CH7007A
Input Data Formats
The XCLK and XCLK* signals are used to latch data from the graphics chip. Data can be latched coincident with
the rising edge of XCLK, falling edge of XCLK, or both edges, depending upon register settings of XCM and MCP.
The input data format is shown in
Figure4
. The Pixel Data bus represents an 8 or 12-bit multiplexed data stream,
which contains either RGB or YCrCb formatted data. In IDF settings of 4, 5, 7, 8 and 9, the input data rate is 2X
pixel clock, and each pair of Pn values (e.g., P0a and P0b) will contain a complete pixel, encoded as shown in the
tables below. When the input is YCrCb, the color-difference data will be transmitted at half the data rate of the lumi-
nance data, with the sequence being set as Cb0, Y0, Cr0, Y1 where Cb0,Y0,Cr0 refers to co-sited luminance and
color-difference samples — and the following Y1 byte refers to the next luminance sample, per CCIR656 standards.
However, the clock frequency is dependent upon the current mode, not 27MHz, as specified in CCIR656
.
Figure 4: Non-multiplexed Data Transfers
Table 3. RGB 8-bit Multiplexed Mode
IDF#
Format
Pixel#
Bus Data
7
RGB 5-6-5
P0b
R0[4]
R0[3]
R0[2]
R0[1]
R0[0]
G0[5]
G0[4]
G0[3]
8
RGB 5-5-5
P0b
x
R0[4]
R0[3]
R0[2]
R0[1]
R0[0]
G0[4]
G0[3]
P0a
G0[2]
G0[1]
G0[0]
B0[4]
B0[3]
B0[2]
B0[1]
B0[0]
P1a
G1[2]
G1[1]
G1[0]
B1[4]
B1[3]
B1[2]
B1[1]
B1[0]
P1b
R1[4]
R1[3]
R1[2]
R1[1]
R1[0]
G1[5]
G1[4]
G1[3]
P0a
G0[2]
G0[1]
G0[0]
B0[4]
B0[3]
B0[2]
B0[1]
B0[0]
P1a
G1[2]
G1[1]
G1[0]
B1[4]
B1[3]
B1[2]
B1[1]
B1[0]
P1b
x
R1[4]
R1[3]
R1[2]
R1[1]
R1[0]
G1[4]
G1[3]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
XCLK
(XCM=01)
D[11:0]
P0b
P1a
P1b
P2a
P0a
P2b
XCLK*
(XCM=01)
XCLK
(XCM=00)
XCLK*
(XCM=00)
HS
DS / BCO
SAV
(DSEN=0)
When DSEN=1(bit 4 of register 1Ch), SAV should be set to 11d.
相關PDF資料 |
PDF描述 |
|---|---|
| CH7007A-T | DIGITAL PC TO TV ENCODER WITH MACROVISION |
| CH7007A-V | DIGITAL PC TO TV ENCODER WITH MACROVISION |
| CH7008A | Digital PC to TV Encoder Features |
| CH7008A-T | Digital PC to TV Encoder Features |
| CH7008A-V | Digital PC to TV Encoder Features |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CH7007A-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DIGITAL PC TO TV ENCODER WITH MACROVISION |
| CH7007A-V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DIGITAL PC TO TV ENCODER WITH MACROVISION |
| CH7008A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder Features |
| CH7008A-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder Features |
| CH7008A-V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder Features |
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