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參數(shù)資料
| 型號： | CH7007A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | DIGITAL PC TO TV ENCODER WITH MACROVISION |
| 中文描述： | 電腦數(shù)字電視編碼器和通過Macrovision |
| 文件頁數(shù)： | 5/49頁 |
| 文件大小： | 278K |
| 代理商： | CH7007A |
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201-0000-002 Rev. 2.7, 08/23/2000
5
CHRONTEL
CH7007A
44-Pin
PLCC
44-Pin
TQFP
Type
Symbol
Description
32
26
In/Out
SD
Serial Data Input/Output
This pin functions as the serial data pin of the I
2
C interface port, and
uses the DVDD supply.
(see the I
2
C Port Operation section for details)
Serial Clock Input
This pin functions as the serial clock pin of the I
2
C interface port, and
uses the DVDD supply.
(see the I
2
C Port Operation section for details)
Reset* Input
When this pin is low, the CH7007 is held in the power-on reset
condition. When this pin is high, the device operates normally and reset
is controlled through the I
2
C register.
33
27
In
SC
35
29
In
RESET*
38
32
In
XI/FIN
Crystal Input/External Reference Input
A parallel resonance 14.31818MHz crystal should be attached
between this pin and XO. However, an external CMOS clock can be
attached to XI/FIN.
Crystal Output
A parallel resonance 14.31818MHz +20ppm crystal should be
attached between this pin and XI/FIN. However, if an external CMOS
clock is attached to XI/FIN, XO should not be connected.
Data start (input)/Buffered Clock (output)
In normal operating modes, when configured as an input, the rising
edge of this signal identifies the first active pixel of data for each
active line. The level is 0 to DVDD2, with VREF as the threshold level.
39
33
Out
XO
41
35
In/Out
DS/BCO
When configured as an output this pin provides a buffered clock
output, driven by the DVDD supply. The output clock can be selected
using the BCO register (17th) (see Registers and Programing).
43
37
Out
P-OUT
Pixel Clock Output
This pin provides a pixel clock signal to the VGA controller (adjustable as
1X, 2X and 3X) and is driven from the DVDD2 supply. This clock will only
be provided in master clock modes, and will be tri-stated otherwise, (see
the section on Digital Video Interface and Registers and Programming
for more details). The capacitive loading on this pin should be kept to a
minimum.
Digital Supply Voltage
11,22,36
5,16,30
Power
DVDD
14,24,34,
42
8,18,28,
36
Power
DGND
Digital Ground
25,29
19,23
Power
GND
DAC
31
25
Power
VDD
DAC Supply Voltage
37
31
Power
AVDD
PLL Supply Voltage
40
34
Power
AGND
PLL Ground
44
38
Power
DVDD2
I/O SUPPLY VOLTAGE
Digital supply voltage for the P-OUT
Table 1. Pin Descriptions
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CH7007A-T | DIGITAL PC TO TV ENCODER WITH MACROVISION |
| CH7007A-V | DIGITAL PC TO TV ENCODER WITH MACROVISION |
| CH7008A | Digital PC to TV Encoder Features |
| CH7008A-T | Digital PC to TV Encoder Features |
| CH7008A-V | Digital PC to TV Encoder Features |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CH7007A-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DIGITAL PC TO TV ENCODER WITH MACROVISION |
| CH7007A-V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DIGITAL PC TO TV ENCODER WITH MACROVISION |
| CH7008A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder Features |
| CH7008A-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder Features |
| CH7008A-V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder Features |
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