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參數(shù)資料
| 型號(hào)： | CH7005C-V |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Digital PC to TV Encoder with Macrovision |
| 中文描述： | 數(shù)碼電腦電視編碼器和通過Macrovision |
| 文件頁數(shù)： | 40/49頁 |
| 文件大小： | 338K |
| 代理商： | CH7005C-V |
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CHRONTEL
CH7005C
40
201-0000-025 Rev 2.1, 8/2/99
Register Descriptions
(continued)
Figure 26: Luma Transfer Function at different contrast enhancement settings.
PLL Overflow Register
Symbol: MNE
Address: 13H
Bits: 5
The PLL Overflow Register contains the MSB bits for the ‘M’ and ‘N’ values, which will be described in the PLL-
M and PLL-N registers, respectively. The reserved bits should not be written to.
PLL M Value Register
Symbol: PLLM
Address: 14H
Bits: 8
The PLL M value register determines the division factor applied to the frequency reference clock before it is input to
the PLL phase detector when the CH7005 is operating in master or pseudo-master clock mode. In slave mode, an
external pixel clock is used instead of the frequency reference, and the division factor is determined by the
XCM[3:0] value. This register contains the lower 8 bits of the complete 9-bit M value.
Bit:
Symbol:
7
6
5
4
Reserved
3
Reserved
2
N9
1
N8
0
M8
Type:
Default:
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Bit:
7
M7
6
M6
5
M5
4
M4
3
M3
2
M2
1
M1
0
M0
Symbol:
Type:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default:
0
1
0
0
0
0
0
1
0
32
64
96
128
160
192
224
256
0
32
64
96
128
160
192
224
256
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