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參數(shù)資料
| 型號： | CH7005C-V |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Digital PC to TV Encoder with Macrovision |
| 中文描述： | 數(shù)碼電腦電視編碼器和通過Macrovision |
| 文件頁數(shù)： | 32/49頁 |
| 文件大?。?/td> | 338K |
| 代理商： | CH7005C-V |
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CHRONTEL
CH7005C
32
201-0000-025 Rev 2.1, 8/2/99
Flicker Filter Register
Symbol: FFR
Address: 01H
Bits: 6
The flicker filter register provides for adjusting the operation of the various filters used in rendering the on-screen
image. Adjusting settings between minimal and maximal values enables optimization between sharpness and flicker
content. The FC[1:0] bits determine the settings for the chroma channel. The FT[1:0] bits determine the settings for
the text enhancement circuit. The FY[1:0] bits determine the settings for the luma channel. In addition, the Chroma
channel filtering includes a setting to enable the chroma dot crawl reduction circuit.
Note:
When writing to register O1H, FY[1:0] is bits 3:2. FT[1:0] is bits 1:0. When reading from the register O1H, FY
[1:0] is bits 1:0 and FT[1:0] is bits 3:2.
Register Descriptions
(continued)
VOS[1:0]
00
01
10
11
Output Format
PAL
NTSC
PAL-M
NTSC-J
Bit:
Symbol:
7
6
5
FC1
4
FC0
3
FY1
2
FY0
1
FT1
0
FT0
Type:
Default:
R/W
R/W
R/W
R/W
R/W
R/W
1
1
0
0
1
0
Table 17. Flicker Filter Settings
FY[1:0]
Settings for Luma Channel
00
Minimal Flicker Filtering
01
Slight Flicker Filtering
10
Maximum Flicker Filtering
11
Invalid
FT[1:0]
Settings for Text Enhancement Circuit
00
Maximum Text Enhancement
01
Slight Text Enhancement
10
Minimum Text Enhancement
11
Invalid
FC[1:0]
Settings for Chroma Channel
00
Minimal Flicker Filtering
01
Slight Flicker Filtering
10
Maximum Flicker Filtering
11
Enable Chroma DotCrawl Reduction
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