
201-0000-025 Rev 2.1, 8/2/99
41
CHRONTEL
Register Descriptions
(continued)
CH7005C
PLL N Value Register
Symbol: PLLN
Address: 15H
Bits: 8
The PLL N value register determines the division factor applied to the VCO output before being applied to the PLL
phase detector, when the CH7005 is operating in master or pseudo-master mode. In slave mode, the value of ‘N’ is
always 1. This register contains the lower 8 bits of the complete 10-bit N value. The pixel clock generated in a
master and pseudo-master modes is calculated according to the equation below:
Fpixel = Fref* [(N+2) / (M+2)]
When using a 14.318 MHz frequency reference, the required M and N values for each mode are shown in the table
below
Buffered Clock Output Register
Symbol: BCO
Address: 17H
Bits: 6
When this pin is selected to be an output, the buffered clock output register determines which clock is selected to be
output at the DS/BCO clock output pin and what frequency value is output when a VCO derived signal is out-
put.The tables below show the possible outputs.
Bit:
7
N7
6
N6
5
N5
4
N4
3
N3
2
N2
1
N1
0
N0
Symbol:
Type:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default:
1
0
0
0
0
0
0
0
Table 24. M and N Values for Each Mode
Mode
VGA Resolution, TV
Standard, Scaling Ratio
N 10-
bits
M 9-
bits
Mode
VGA Resolution, TV
Standard, Scaling Ratio
640X480, PAL, 5:6
640X480, NTSC, 1:1
640X480, NTSC, 7:8
640X480, NTSC, 5:6
800X600, PAL, 1:1
800X600, PAL, 5:6
800X600, PAL, 3:4
800X600, NTSC, 5:6
800X600, NTSC, 3:4
800X600, NTSC, 7:10
720X576, PAL, 1:1
720X480, NTSC, 1:1
800X500, PAL, 1:1
640X400, NTSC, 1:1
N 10-
bits
9
110
126
190
647
86
284
94
62
302
31
31
242
2
M 9-
bits
3
63
63
89
313
33
103
33
19
89
33
33
197
2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
512x384, PAL, 5:4
512x384, PAL, 1:1
512X384, NTSC, 5:4
512X384, NTSC, 1:1
720X400, PAL, 5:4
720X400, PAL, 1:1
720X400, NTSC, 5:4
720X400, NTSC, 1:1
640X400, PAL, 5:4
640X400, PAL, 1:1
640X400, NTSC, 5:4
640x400, NTSC, 1:1
640X400, NTSC, 7:8
640X480, PAL, 5:4
640X480, PAL, 1:1
20
9
126
110
53
339
106
70
108
9
94
22
190
20
9
13
4
89
63
26
138
63
33
61
3
63
11
89
13
4
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Bit:
Symbol:
7
6
5
SHF2
4
SHF1
3
SHF0
2
SCO2
1
SCO1
0
SCO0
Type:
Default:
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0