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參數(shù)資料
| 型號： | CDRM622 |
| 廠商： | Lineage Power |
| 英文描述： | 622 Mbits/s Multichannel Digital Timing Recovery(622M位/秒 多通道數(shù)字定時恢復) |
| 中文描述： | 622 Mbits /秒多通道數(shù)字定時恢復（622M位/秒多通道數(shù)字定時恢復） |
| 文件頁數(shù)： | 9/14頁 |
| 文件大?。?/td> | 278K |
| 代理商： | CDRM622 |
Data Sheet
June 1999
CDRM622
622 Mbits/s Multichannel Digital Timing Recovery Macrocell
9
Lucent Technologies Inc.
Simulation Interface
(continued)
5-5838 (F).er.1
Notes:
During PLL BYPASS mode, TSTCLK is asynchronous to the REF78 input of the CDRM622; therefore, test resets (RESETTN and RESETRN)
were added to allow establishing a relationship between the internally generated 77.76 MHz clocks and the reference clocks.
RESETRN allows synchronization of the 77.76 MHz recovered clocks in the receiver.
RESETTN allows synchronization of the 77.76 MHz clock internal to the transmitter.
TSTCLK should be stopped high while the resets change but needs to toggle at least four clock cycles while resets are active.
Figure 6. Synchronization of CDRM622 Generated Clocks During Bypass Mode
Test Interface
Boundary Scan
In order to avoid loading the high-speed data signals unnecessarily, access has been provided through the macro-
cell. The state of the input pads can be monitored at buffered test outputs. The state of the output pads can be con-
trolled through a multiplexer built into the macrocell data path.
Table 3. System Test Signals
Signal Name
Type
Description
BSIPAD[(n – 1):0]
O
Provides buffered monitor points reflecting state of the 622.08 Mbits/s device
input pads for use in boundary scan.
Provides access to 622.08 Mbits/s output pads for boundary scan. Output
boundary-scan multiplexers are built into the macrocell.
(Active-High).
Enables boundary-scan values to control 622.08 MHz output
device pins.
(Active-High).
Enables 622.08 Mbits/s loopback mode. All transmit outputs are
directed into the receivers. Overrides individual channel loopback controls.
(Active-High).
Enables 622.08 Mbits/s loopback mode on a per-channel basis.
BSOPAD[(n – 1):0]
I
BSCANEN
I
LOOPBKEN
I
LOOPBKCH[(n – 1):0]
I
8A
96
E4
LD[(n – 1):0]X[7:0]
HDOUT[(n – 1):0]
TSTCLK
REF78
RESETTN
RESETRN
LCKR[(n – 1):0]
TSTCLK STOPPED FOR A MINIMUM OF TEN CLOCK CYCLES
LCK78
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