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參數(shù)資料
| 型號(hào)： | CDRM622 |
| 廠商： | Lineage Power |
| 英文描述： | 622 Mbits/s Multichannel Digital Timing Recovery(622M位/秒 多通道數(shù)字定時(shí)恢復(fù)) |
| 中文描述： | 622 Mbits /秒多通道數(shù)字定時(shí)恢復(fù)（622M位/秒多通道數(shù)字定時(shí)恢復(fù)） |
| 文件頁數(shù)： | 1/14頁 |
| 文件大?。?/td> | 278K |
| 代理商： | CDRM622 |
Data Sheet
June 1999
CDRM622
622 Mbits/s Multichannel Digital Timing Recovery
Features
I
Receives scrambled serial data at STS-12/STM-4
(622.08 Mbits/s) rate.
I
Demultiplexes serial data to 77.76 Mbytes/s paral-
lel byte wide data with aligned 77.76 MHz clock.
I
Synthesizes 622.06 MHz clock with on-chip PLL,
requiring only 77.76 MHz input reference clock and
one external resistor.
I
Multiplexes parallel 77.76 Mbytes/s data to
622 Mbits/s serial data for transmission.
I
Incorporates n = 1 to 16 channels with modular
design. Implemented in Lucent Technologies
Microelectronics Group HL250C technology.
I
Meets type B jitter tolerance specification of ITU-T
Recommendation G.958.
I
Sources stable clock in absence of data transitions
once the clock synthesizer has acquired lock.
I
Uses single, low-voltage (3.3 V ± 5%) supply.
I
Includes built-in test circuitry such as high-speed
loopback of transmit data into receiver.
I
IDDQ compatible.
I
Powers down the receiver on per-channel basis.
I
Allows JTAG access to high-speed data paths.
Description
The CDRM622 provides a physical medium for high-
speed asynchronous serial data transfer between
ASIC devices. Devices can be on the same PC-
board, or on separate boards connected across a
backplane, or connected by cables. The macrocell is
intended for, but not limited to, terminal equipment in
SONET/SDH and ATM systems.
The macrocell consists of three functional blocks.
The receiver accepts 622.08 Mbits/s serial data.
Based on data transitions, the receiver selects an
appropriate 622 MHz clock phase for each channel
to retime the data, then demultiplexes down to
77.76 Mbytes/s parallel bytes and a 77.76 MHz clock.
The transmitter operates in the reverse direction.
77.76 Mbytes/s parallel bytes are multiplexed up to
662.08 Mbits/s serial data for off-chip communica-
tion.
The clock synthesizer generates the necessary
622.08 MHz clock for operation from a 77.76 MHz
reference. Figure 1 illustrates the function of the mac-
rocell.
The hard macrocell can be supplied for up to 16 data
channels. Multiple macrocells can be used on a sin-
gle device. The macrocell is intended to be used with
high-speed differential I/O buffers for the 622 Mbits/s
serial data streams and the 77.76 MHz reference
clock. Common selections are low-voltage differential
swing (LVDS) or PECL. The I/O buffers are part of
our standard-cell ASIC library and are not included in
the macrocell to allow for flexibility.
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