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參數(shù)資料
| 型號： | CD4012 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Dual 4-Input NOR(NAND) Gate |
| 中文描述： | 雙4輸入或非（閃存）門 |
| 文件頁數(shù)： | 4/6頁 |
| 文件大?。?/td> | 113K |
| 代理商： | CD4012 |
AC Electrical Characteristics
*
T
A
e
25
§
C, C
L
e
15 pF, and input rise and fall times
e
20 ns. Typical
temperature coefficient for all values of V
DD
e
0.3%/
§
C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CD4002M
t
PHL
Propagation Delay Time
High to Low Level
V
DD
e
5.0V
V
DD
e
10V
V
DD
e
5.0V
V
DD
e
10V
V
DD
e
5.0V
V
DD
e
10V
V
DD
e
5.0V
V
DD
e
10V
Any Input
35
25
50
40
ns
ns
t
PLH
Propagation Delay Time
Low to High Level
35
25
50
40
ns
ns
t
THL
Transition Time High
to Low Level
65
35
175
75
ns
ns
t
TLH
Transition Time Low
to High Level
65
35
125
70
ns
ns
C
IN
CD4002C
Input Capacitance
5.0
pF
t
PHL
Propagation Delay Time
High to Low Level
V
DD
e
5.0V
V
DD
e
10V
V
DD
e
5.0V
V
DD
e
10V
V
DD
e
5.0V
V
DD
e
10V
V
DD
e
5.0V
V
DD
e
10V
Any Input
35
25
120
65
ns
ns
T
PLH
Propagation Delay Time
Low to High Level
35
25
80
55
ns
ns
t
THL
Transition Time High
to Low Level
65
35
300
125
ns
ns
t
TLH
Transition Time Low
to High Level
65
35
200
115
ns
ns
C
IN
Input Capacitance
5.0
pF
*
AC Parameters are guaranteed by DC correlated testing.
AC Electrical Characteristics
*
T
A
e
25
§
C, C
L
e
15 pF, and input rise and fall times
e
20 ns. Typical
temperature coefficient for all values of V
DD
e
0.3%/
§
C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CD4012M
t
PHL
Propagation Delay Time
High to Low Level
V
DD
e
5.0V
V
DD
e
10V
V
DD
e
5.0V
V
DD
e
10V
V
DD
e
5.0V
V
DD
e
10V
V
DD
e
5.0V
V
DD
e
10V
Any Input
50
25
75
40
ns
ns
t
PLH
Propagation Delay Time
Low to High Level
50
25
75
40
ns
ns
t
THL
Transition Time High
to Low Level
75
50
125
75
ns
ns
t
TLH
Transition Time Low
to High Level
75
40
100
60
ns
ns
C
IN
CD4012C
Input Capacitance
5.0
pF
t
PHL
Propagation Delay Time
High to Low Level
V
DD
e
5.0V
V
DD
e
10V
V
DD
e
5.0V
V
DD
e
10V
V
DD
e
5.0V
V
DD
e
10V
V
DD
e
5.0V
V
DD
e
10V
Any Input
50
25
100
50
ns
ns
T
PLH
Propagation Delay Time
Low to High Level
50
25
100
50
ns
ns
t
THL
Transition Time High
to Low Level
75
50
150
100
ns
ns
t
TLH
Transition Time Low
to High Level
75
40
125
75
ns
ns
C
IN
Input Capacitance
5.0
pF
*
AC Parameters are guaranteed by DC correlated testing.
Note 1:
‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature
Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual
device operation.
4
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| CD4012C | Single 2-Input Positive-NOR Gate 5-SC70 -40 to 85 |
| CD4012M | Single 2-Input Positive-NOR Gate 5-SOT -40 to 85 |
| CD4012BMS | CMOS NAND Gates |
| CD4013BCJ | Single Inverter 5-SOT-23 -40 to 85 |
| CD4013BCN | Single Inverter 5-SOT-23 -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CD40129BD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| CD40129BE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| CD40129BF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| CD4012A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:CMOS NAND Gates |
| CD4012AD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
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