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參數(shù)資料
| 型號(hào)： | CAT9534HV4I-GT2 |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 12/14頁(yè) |
| 文件大小： | 0K |
| 描述： | IC I/O EXPANDER 8BIT 16-TQFN |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 接口： | I²C，SM 總線 |
| 輸入/輸出數(shù)： | 8 |
| 中斷輸出： | 是 |
| 頻率 - 時(shí)鐘： | 400kHz |
| 電源電壓： | 2.3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-WQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 16-TQFN（4x4） |
| 包裝： | 帶卷 (TR) |
| 包括： | POR |
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CAT9534
http://onsemi.com
7
Functional Description
CAT9534’s general purpose input/ output (GPIO)
peripherals provide up to eight I/O ports, controlled through
an I2C compatible serial interface.
The CAT9534 supports the I2C Bus data transmission
protocol. This I2C Bus protocol defines any device that
sends data to the bus to be a transmitter and any device
receiving data to be a receiver. The transfer is controlled by
the Master device which generates the serial clock and all
START and STOP conditions for bus access. The CAT9534
operates as a Slave device. Both the Master device and Slave
device can operate as either transmitter or receiver, but the
Master device controls which mode is activated.
I2C Bus Protocol
The features of the I2C bus protocol are defined as follows:
1. Data transfer may be initiated only when the bus is
not busy.
2. During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock line is high
will be interpreted as a START or STOP condition
(Figure 6).
START and STOP Conditions
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of SDA
when SCL is HIGH. The CAT9534 monitors the SDA and
SCL lines and will not respond until this condition is met.
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
Device Addressing
After the bus Master sends a START condition, a slave
address byte is required to enable the CAT9534 for a read or
write operation. The four most significant bits of the slave
address are fixed as binary 0100 and the next three bits are
its individual address bits (Figure 7).
The address bits A2, A1 and A0 are used to select which
device is accessed from maximum eight devices on the same
bus. These bits must compare to their hardwired input pins.
The 8th bit following the 7bit slave address is the R/W bit
that specifies whether a read or write operation is to be
performed. When this bit is set to “1”, a read operation is
initiated, and when set to “0”, a write operation is selected.
Following the START condition and the slave address
byte, the CAT9534 monitors the bus and responds with an
acknowledge (on the SDA line) when its address matches
the transmitted slave address. The CAT9534 then performs
a read or a write operation depending on the state of the R/W
bit.
START
CONDITION
STOP
CONDITION
SDA
SCL
Figure 6. START/STOP Condition
0
1
0
A2
A1
A0
SLAVE ADDRESS
FIXED
PROGRAMMABLE
HARDWARE
SELECTABLE
Figure 7. CAT9534 Slave Address
R/W
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CAT9554AHV4I-GT2 | IC I/O EXPANDER I2C SMBUS 16TQFN |
| CAT9554AHV4I-T2 | IC I/O EXPANDER I2C/SMBUS 16TQFN |
| CAT9555HV6I-G | IC I/O EXPANDER 16BI 2C 24TQFN |
| CC-2401K2A-CS | MODEM 2400BAUD SECURE 3.3V |
| CC-2434K2-CS5 | MODEM FAX 33K 5V |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CAT9534HV4I-GT2-CUT TAPE | 制造商:ON 功能描述:CAT9534 Series 2.3 to 5.5 V 8-bit 8 I/O I? and SMBus I/O Port - TQFN-16 |
| CAT9534WI-GT2 | 功能描述:接口-I/O擴(kuò)展器 8B I2C &SMBus I/O PORT RoHS:否 制造商:NXP Semiconductors 邏輯系列: 輸入/輸出端數(shù)量: 最大工作頻率:100 kHz 工作電源電壓:1.65 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:HVQFN-16 封裝:Reel |
| CAT9534YI-G | 制造商:Catalyst Semiconductor 功能描述: |
| CAT9534YI-GT2 | 功能描述:接口-I/O擴(kuò)展器 8B I2C &SMBus I/O PORT RoHS:否 制造商:NXP Semiconductors 邏輯系列: 輸入/輸出端數(shù)量: 最大工作頻率:100 kHz 工作電源電壓:1.65 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:HVQFN-16 封裝:Reel |
| CAT9552HV6GI | 制造商:Rochester Electronics LLC 功能描述: 制造商:Catalyst Semiconductor 功能描述: |
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