參數(shù)資料
型號(hào)： C1851BCU
廠商： NEC Corp.
英文描述： I2C BUS-COMPATIBLE US MTS PROCESSING LSI
中文描述： I2C總線兼容美國(guó)的多邊貿(mào)易體制處理LSI
文件頁數(shù)： 49/60頁
文件大?。?/td> 447K
代理商： C1851BCU
53
PC1851B
Data Sheet S13417EJ2V0DS00
(6/8)
Parameter
Symbol
Test Conditions
User Mode Note
Inter-mode DC offset 2
VDOF2
VDOF2 = VST – VMute
Mute
VST : DC voltage at LOT and ROT pins
to
User mode : Stereo
Stereo
NDT pin: 6 V DC is applied.
VMute : DC voltage at LOT and ROT pins
User mode : Mute (write register 06H, D1: 0)
NDT pin: 6 V DC is applied.
Inter-mode DC offset 3
VDOF3
VDOF3 = VSAP – VMute
Mute
VSAP : DC voltage at LOT and ROT pins
to
User mode : SAP1
SAP1
NDT pin: 6 V DC is applied.
VMute : DC voltage at LOT and ROT pins
User mode : Mute (write register 06H, D1: 0)
NDT pin: 6 V DC is applied.
Inter-mode DC offset 4
VDOF4
VDOF4 = VMONO – VMute
Mute
VMONO : DC voltage at LOT and ROT pins
to
User mode : External input
External
NDT pin: 6 V DC is applied.
input
VMute : DC voltage at LOT and ROT pins
User mode : Mute (write register 06H, D1: 0)
NDT pin: 6 V DC is applied.
Surround output
VSR1L
VSR1L = 20 log (VL1
÷ VEL)
External input 1
characteristics 1
VL1: Output voltage of LOT pin
External input 2
VEL: Input voltage of EL1, EL2 pins (100 Hz, 150 mVrms)
ER1, ER2 pins: No signal
Surround: ON (Subaddress 04H, Bit D6: 1)
Surround output
VSR2L
VSR2L : 20 log (VL2
÷ VEL)
characteristics 2
VL2: Output voltage of LOT pin
VEL: Input voltage of EL1, EL2 pins (1 kHz, 150 mVrms)
ER1, ER2 pins: No signal
Surround: ON (Subaddress 04H, Bit D6: 1)
Surround output
VSR3L
VSR3L : 20 log (VL3
÷ VEL)
characteristics 3
VL3: Output voltage of LOT pin
VEL: Input voltage of EL1, EL2 pins (10 kHz, 150 mVrms)
ER1, ER2 pins: No signal
Surround: ON (Subaddress 04H, Bit D6: 1)
Surround output
VSR4R
VSR4R : 20 log (VR
÷ VEL)
characteristics 4
VR: Output voltage of ROT pin
VEL: Input voltage of EL1, EL2 pins (1 kHz, 150 mVrms)
ER1, ER2 pins: No signal
Surround: ON (Subaddress 04H, Bit D6: 1)
Note
For details about the User Mode, refer to 5. MODE MATRIX.
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