參數(shù)資料
型號(hào): C1851BCU
廠商: NEC Corp.
英文描述: I2C BUS-COMPATIBLE US MTS PROCESSING LSI
中文描述: I2C總線兼容美國的多邊貿(mào)易體制處理LSI
文件頁數(shù): 27/60頁
文件大?。?/td> 447K
代理商: C1851BCU
33
PC1851B
Data Sheet S13417EJ2V0DS00
(4) Input select
The signal to be input to the selector block in the
PC1851B can be selected by the data of bits D4 to D6 of
subaddress 06H. The selected signal is output from the LOT, ROT, FOL and FOR pins.
For the combination of bits for the signal to be selected, refer to 6. SELECTOR TABLE.
Input select 1 :
switches the TV signal (signal with the audio multiple signal processed in the
PC1851B)
and external inputs 1 and 2 (signal input from EL1, EL2, ER1 and ER2 pins).
Input select 2 :
switches the stereo signal and monaural signal.
Figure 4-4.
Input Select
Note
When SAP2 is selected by switching SAP1/SAP2, the L+R signal and SAP signal are composite to be
output.
D7
00
01
10
11
06H
Automatic
increment
Input select 1
Input select 2
SAP1/SAP2
switch
Stereo/SAP
switch
D6
D5
D4
D3
D2
D1
D0
TV signal
External input 1
External input 2
Setting prohibited
Input select 1
0
1
L-channel signal
Note
R-channel signal
Monaural (L+R) signal
L-channel output
(LOT, FOL pins)
R-channel output
(ROT, FOR pins)
Input select 2
Forced monaural
ON/OFF
Mute
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