Mobile Intel
Celeron Processor (0.18μ) in BGA2 and Micro-PGA2 Packages
Datasheet
Order Number#249563-001
78
Appendix A: PLL RLC Filter
Specification
A.1
Introduction
All mobile Intel Celeron processors have internal PLL clock generators, which are analog in
nature and require quiet power supplies for minimum jitter. Jitter is detrimental to a system; it
degrades external I/O timings as well as internal core timings (i.e. maximum frequency). In
mobile Intel Celeron processors in the BGA1 and μPGA1 packages, the power supply filter was
specified as an external LC network. This remains largely the same for the mobile Intel Celeron
processor in the BGA2 and μPGA2 packages. However, due to increased current flow, the value
of the inductor has to be reduced, thereby requiring new components. The general desired
topology is shown in Figure 4. Excluded from the external circuitry are parasitics associated with
each component.
A.2
Filter Specification
The function of the filter is two fold. It protects the PLL from external noise through low-pass
attenuation. It also protects the PLL from internal noise through high-pass filtering. In general,
the low-pass description forms an adequate description for the filter.
The AC low-pass specification, with input at V
CCT
and output measured across the capacitor, is as
follows:
< 0.2-dB gain in pass band
< 0.5-dB attenuation in pass band < 1 Hz (see DC drop in next set of requirements)
34-dB attenuation from 1 MHz to 66 MHz
28-dB attenuation from 66 MHz to core frequency
The filter specification (AC) is graphically shown in Figure 25.
Other requirements:
Use a shielded type inductor to minimize magnetic pickup
The filter should support a DC current of at least 30 mA
The DC voltage drop from V
CCT
to PLL1 should be less than 60 mV, which in practice implies
series resistance of less than 2
. This also means that the pass band (from DC to 1Hz)
attenuation below 0.5 dB is for V
CCT
= 1.1V and below 0.35 dB for V
CCT
= 1.5V.