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參數(shù)資料
| 型號(hào)： | BU7345HFV |
| 元件分類： | XO, clock |
| 英文描述： | OTHER CLOCK GENERATOR, PDSO6 |
| 封裝： | SOF-6 |
| 文件頁數(shù)： | 3/5頁 |
| 文件大小： | 123K |
| 代理商： | BU7345HFV |
3/4
○
Block diagram,
pin function
Power supply voltage VDD=3.3V,Ta=25
℃
,IN=27.0000MHz,
38.0000MHz output (OUT=IN
×
(76/27)/2) as SEL=L,
36.0000MHz output (OUT=IN
×
(8/3)/2) as SEL=H
●
Cautions
on
use
（
BU7345
HFV
）
Basicall
y,
mount
ICs
to
the
printed
circuit
board for use. (If the ICs are not mounted to the printed circuit board, the characteristics of ICs may not be fully
demonstrated.)
Mount 0.1
F capacitors in the vicinity of the IC PINs between 1PIN (VDD) and 2PIN (VSS), respectively.
Depending on the conditions of the printed circuit board, mount an additional electrolytic capacitor between the power
supply and GND terminal.
For EMI protection, it is effective to put ferrite beads in the origin of power supply to be fed to BU7345HFV from the
printed circuit board or to insert a capacitor (of 1
or less), which bypasses high frequency desired, between the power
supply and the GND terminal.
When power is first supplied to the CMOS IC, it is possible that the internal logic may be unstable and rush current may
flow instantaneously. Therefore, give special consideration to power coupling capacitance, power wiring, width of GND
wiring, and routing of connections.
REV. A
PIN No.
PIN Name
Function
1
VDD
Power supply
2
VSS
GND
3
OUT
Clock output terminal (SEL=L
：
38.0000MHz, SEL=H
：
36.0000MHz)
4
OE
Power down (L
：
disable, H
：
enable),
Equipment with pull-down function (Typ.100k
Ω
)
Output fixed to L at disable
SEL pin(L
：
38.0000MHz, H
：
36.0000MHz),
Equipment with pull-down function (Typ.100k
Ω
)
5
SEL
6
IN
Clock input pin (27.0000MHz input)
4: OE
6: IN
1: VDD
2: VSS
3: OUT
5: SEL
PLL
1/2
DATA1
DATA2
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