參數(shù)資料
型號： BU-62864B4-150
廠商： DATA DEVICE CORP
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, BGA128
封裝： 0.815 X 0.815 INCH, 0.140 INCH HEIGHT, 1 MM PITCH, BGA-128
文件頁數(shù)： 74/93頁
文件大?。?/td> 504K
代理商： BU-62864B4-150
Data Device Corporation
62743_pre2.DOC
www.ddc-web.com
8-15-01
76
Table 59. CPU Writing Ram or Registers (Shown for 16-Bit, Buffered, Nonzero Wait Mode)
3.3V LOGIC
UNIT
REF
DESCRIPTION
MIN TYP MAX
9)
t13
Data valid hold time following CLOCK IN rising edge (Note 9)
15
ns
t14
IOEN* falling delay to READYD* falling @20 MHz (Notes 6,9)
85
100
115
ns
@16 MHz (Notes 6,9)
110
125
140
ns
@12 MHz (Notes 6,9)
152
167
182
ns
@10 MHz (Notes 6,9)
185
200
215
ns
t15
CLOCK IN rising edge delay to READYD* falling (Note 6)
40
ns
t16
READYD* falling to STRBD* rising release time.
∞
ns
t17
STRBD* rising edge delay to IOEN* rising edge and READYD*
rising edge (Note 6)
40
ns
t18
STRBD* high hold time from READYD* rising
0
ns
INTERFACE TO MIL-STD-1553 BUS
Figure
illustrates the interface between the PCI Enhanced Mini-ACE, and a
MIL-STD-1553 bus.
Connections for both direct (short stub) and transformer
(long stub) coupling, as well as the peak-to-peak voltage levels at various points
(when transmitting), are indicated in the diagram.
Figure 13. PCI Enhanced Mini-ACE Interface to MIL-STD-1553 Bus.
相關(guān)PDF資料
PDF描述
BU-65142D2-110W 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78
BU-65142D2-140W 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78
BU-65142F2-190W 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP78
BU-65170S3-202 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70
BU-65171G3-302 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70
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