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參數(shù)資料
| 型號(hào)： | BU-62743B4-110L |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, BGA128 |
| 封裝： | 0.815 X 0.815 INCH, 0.140 INCH HEIGHT, 1 MM PITCH, BGA-128 |
| 文件頁數(shù)： | 66/93頁 |
| 文件大?。?/td> | 504K |
| 代理商： | BU-62743B4-110L |
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Data Device Corporation
62743_pre2.DOC
www.ddc-web.com
8-15-01
69
MISCELLANEOUS
1553 CLOCK INPUT
The PCI Enhanced Mini-ACE decoder is capable of operating from a 10, 12, 16,
or 20 MHz clock input. The selection of the clock input frequency may be chosen
by one of either two methods. For all versions, the clock frequency may be
specified by means of the host processor writing to Configuration Register #6.
With the second method, which is applicable only for the versions incorporating
4K (but not 64K) words of internal RAM, the clock frequency may be specified by
means of the input signals that are otherwise used as the A15 and A14 address
lines.
ENCODER/DECODERS
For the selected clock frequency, there is internal logic to derive the necessary
clocks for the Manchester encoder and decoders. For all clock frequencies, the
decoders sample the receiver outputs on both edges of the input clock. By in
effect doubling the decoders’ sampling frequency, this serves to widen the
tolerance to zero-crossing distortion, and reduce the bit error rate.
For interfacing to fiber optic transceivers (e.g., for MIL-STD-1773 applications),
the decoders are capable of operating with single-ended, rather than double-
ended, input signals. For applications involving the use of single-ended
transceivers, it is suggested that you contact the factory at DDC regarding a
transceiverless version of the PCI Enhanced Mini-ACE.
TIME TAG
The PCI Enhanced Mini-ACE includes an internal read/writable Time Tag
Register.
This register is a CPU read/writable 16-bit counter with a
programmable resolution of either 2, 4, 8, 16, 32, or 64
s per LSB. Another
option allows software controlled incrementing of the Time Tag Register. This
supports self-test for the Time Tag Register. For each message processed, the
value of the Time Tag Register is loaded into the second location of the
respective descriptor stack entry (“TIME TAG WORD”) for BC/RT/MT modes.
The functionality of the Time Tag Register is compatible with ACE/Mini-ACE
(Plus) includes: the capability to issue an interrupt request and set a bit in the
Interrupt Status Register when the Time Tag Register rolls over FFFF to 0000;
for RT mode, the capability to automatically clear the Time Tag Register
following reception of a Synchronize (without data) mode command, or to load
the Time Tag Register following a Synchronize (with data) mode command.
Additional time tag features supported by the PCI Enhanced Mini-ACE include
the capability for the BC to transmit the contents of the Time Tag Register as the
data word for a Synchronize (with data) mode command; the capability for the
RT to “filter” the data word for the Synchronize with data mode command, by
only loading the Time Tag Register if the LSB of the received data word is “0”; an
instruction enabling the BC Message Sequence Control engine to autonomously
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