參數(shù)資料
型號(hào): BU-62743B4-110L
廠商: DATA DEVICE CORP
元件分類(lèi): 微控制器/微處理器
英文描述: 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, BGA128
封裝: 0.815 X 0.815 INCH, 0.140 INCH HEIGHT, 1 MM PITCH, BGA-128
文件頁(yè)數(shù): 11/93頁(yè)
文件大?。?/td> 504K
代理商: BU-62743B4-110L
Data Device Corporation
62743_pre2.DOC
www.ddc-web.com
8-15-01
19
31 (MSB)
RESERVED - BIT 31 (MSB)
0 (LSB)
RESERVED - BIT 0 (LSB)
Table 14. REG7 Reserved Register
(Write 81Ch)
BIT
DESCRIPTION
31 (MSB)
RESERVED - BIT 31 (MSB)
0 (LSB)
RESERVED - BIT 0 (LSB)
PCI ENHANCED MINI-ACE REGISTER AND MEMORY ADDRESSING
The software interface of the PCI Enhanced Mini-ACE to the host processor
consists of 24 internal operational registers for normal operation, an additional
24 test registers, plus 64K words of shared memory address space. The PCI
Enhanced Mini-ACE’s 4K X 16 or 64K X 17 internal RAM resides in this address
space.
For normal operation, the host processor only needs to access the lower 32
register address locations (00-1F). The next 32 locations (20-3F) should be
reserved, since many of these are used for factory test.
INTERNAL REGISTERS
The address mapping for the PCI Enhanced Mini-ACE registers is
illustrated in Table 15:
Table 15. Address Mapping
ADDRESS LINES
A4
A3
A2
A1
A0
REGISTER
DESCRIPTION / ACCESSIBILITY
0
Interrupt Mask Register #1 (RD/WR)
0
1
Configuration Register #1 (RD/WR)
0
1
0
Configuration Register #2 (RD/WR)
0
1
Start/Reset Register (WR)
0
1
Non-Enhanced BC or RT Command Stack Pointer/Enhanced BC
Instruction List Pointer Register (RD)
0
1
0
BC Control Word/
RT Subaddress Control Word Register (RD/WR)
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