參數(shù)資料
型號(hào): AX88772ALF
廠商: ASIX Electronics Corporation
英文描述: USB 2.0 to 10/100M Fast Ethernet Controller
中文描述: USB 2.0至個(gè)10/100M快速以太網(wǎng)控制器
文件頁(yè)數(shù): 35/45頁(yè)
文件大?。?/td> 778K
代理商: AX88772ALF
ASIX ELECTRONICS CORPORATION
35
AX88772A/AX88172A
Low-pin-count
USB 2.0 to 10/100M Fast Ethernet Controller
9.4.9 SPI Interface Timing
Note: Above diagram only shows setup and hold time relationship of SPI pins in Mode 0. For the remaining 3 modes,
clock polarity is reversed.
SPI Master Controller Timing Table:
Symbol
Description
Fclk
SPI_SCLK clock frequency.
Min
-
Typ
Max
5
Unit
MHz
(Note 3)
Fsys_clk/
(SPIBRR+1)*2
0.5
Tl
Setup time of SPI_SS to the first SPI_SCLK edge.
-
-
Tclk
(Note 3)
Tclk
Tsys_clk
(Note 4)
Tsys_clk
Tsys_clk
Th
Tdly
Hold time of SPI_SS after the last SPI_SCLK edge.
SPI_MOSI data valid time after SPI_SCLK edge.
-
-
0.5
-
-
1
Dsu
Dhd
tl
SPI_MISO data setup time before SPI_SCLK edge.
SPI_MISO data hold time after SPI_SCLK edge.
Minimum idle time between transfers (minimum
SPI_SS high time).
Internal time base period.
2
4
-
-
-
-
Note 5
-
0.5
-
Tclk
Note 3: Fsys_clk is the operating system clock frequency 30Mhz. The SPIBRR is SPI Baud Rate Register.
Tclk = 1/Fclk.
Note 4: Tsys_clk =1/ Fsys_clk =33.33 ns.
Note 5: It will be much greater than 22us because several factors can influence this parameter, such as USB system
utilization, the CBW structure, and High/Full speed ,etc.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AX88772B 制造商:ASIX 制造商全稱:ASIX 功能描述:AX88796C -- 低功耗 SPI或Non-PCI以太網(wǎng)控制器與方案
AX88772BLF 制造商:ASIX Electronics Corporation 功能描述:
AX88772BLI 制造商:ASIX Electronics Corporation 功能描述:
AX88772C 制造商:ASIX 制造商全稱:ASIX 功能描述:AX88796C -- 低功耗 SPI或Non-PCI以太網(wǎng)控制器與方案
AX88772CLF 制造商:ASIX Electronics Corporation 功能描述: