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參數(shù)資料
| 型號： | AX88772ALF |
| 廠商： | ASIX Electronics Corporation |
| 英文描述： | USB 2.0 to 10/100M Fast Ethernet Controller |
| 中文描述： | USB 2.0至個10/100M快速以太網(wǎng)控制器 |
| 文件頁數(shù)： | 16/45頁 |
| 文件大?。?/td> | 778K |
| 代理商： | AX88772ALF |
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ASIX ELECTRONICS CORPORATION
16
AX88772A/AX88172A
Low-pin-count
USB 2.0 to 10/100M Fast Ethernet Controller
GND18A
P
9, 64
Analog Ground for Ethernet PHY and 25Mhz crystal oscillator.
2.2 AX88172A 80-pin Pinout Description
Table 2
: AX88172A 80-pin Pinout Description
Pin Name
Type
Pin No
Pin Description
USB Interface
DP
DM
VBUS
XTL12P
AB
AB
73
72
58
67
USB 2.0 data positive pin.
USB 2.0 data negative pin.
VBUS pin input. Please connect to USB bus power.
12Mhz
±
0.003%crystal or oscillator clock input. This clock is needed for
USB PHY transceiver to operate.
12Mhz crystal or oscillator clock output.
For USB PHY’s internal biasing. Please connect to analog GND through a
resistor (12.1Kohm
±
1%).
Serial EEPROM Interface
EEPROM Clock. EECK is an output clock to EEPROM to provide timing
reference for the transfer of EECS, and EEDIO signals. EECK only drive
high / low when access EEPROM otherwise keep at tri-state and internal
pull-down.
EEPROM Chip Select. EECS is asserted high synchronously with respect
to rising edge of EECK as chip select signal. EECS only drive high / low
when access EEPROM otherwise keep at tri-state and internal pull-down.
EEPROM Data In. EEDIO is the serial output data to EEPROM’s data
input pin and is synchronous with respect to the rising edge of EECK.
EEDIO only drive high / low when access EEPROM otherwise keep at
tri-state and internal pull-up.
Ethernet PHY Interface
25Mhz
±
0.005% crystal or oscillator clock input. This clock is needed for
the embedded 10/100M Ethernet PHY to operate.
25Mhz crystal or oscillator clock output.
Receive data input positive pin for both 10BASE-T and 100BASE-TX.
Receive data input negative pin for both 10BASE-T and 100BASE-TX.
Transmit data output positive pin for both 10BASE-T and 100 BASE-TX
Transmit data output negative pin for both 10BASE-T and 100 BASE-TX
For Ethernet PHY’s internal biasing. Please connect to GND through a
12.1Kohm
±
1% resistor.
Link status LED indicator. This pin drives low continuously when the
Ethernet link is up and drives low and high in turn (blinking) when
Ethernet PHY is in receiving or transmitting state.
Full Duplex and collision detected LED indicator. This pin drives low
when the Ethernet PHY is in full-duplex mode and drives high when in
half duplex mode. When in half duplex mode and the Ethernet PHY
detects collision, it will be driven low (or blinking).
Ethernet speed LED indicator. This pin drives low when the Ethernet PHY
is in 100BASE-TX mode and drives high when in 10BASE-T mode.
Misc. Pins
Chip Reset Input. RESET_N pin is active low. When asserted, it puts the
entire chip into reset state immediately. After completing reset, EEPROM
data will be loaded automatically.
Remote-wakeup trigger from external pin. EXTWAKEUP_N should be
asserted low for more than 2 cycles of 12MHz clock to be effective.
General Purpose Input/ Output Pin 2. This pin is GPIO_2 in MAC mode,
but it will be redefined as RXER (receive error) or GPIO_2 depending on
EEPROM Flag [3]
in PHY mode.
I5/PD/S
I3
XTL12N
RREF
O3
AI
68
71
EECK
B5/PD/
T
45
EECS
B5/PD/
T
46
EEDIO
B5/PU/
T
47
XTL25P
I18
78
XTL25N
RXIP
RXIN
TXOP
TXON
RSET_BG
O18
AB
AB
AB
AB
AO
79
4
5
7
8
1
LINK_LED
O5
26
FDX_LED
O5
24
SPEED_LED
O5
25
RESET_N
I5/PU/S
52
EXTWAKEUP_N
I5/PU/S
30
GPIO_2 / RXER B5/PD
34
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AX88772B | 制造商:ASIX 制造商全稱:ASIX 功能描述:AX88796C -- 低功耗 SPI或Non-PCI以太網(wǎng)控制器與方案 |
| AX88772BLF | 制造商:ASIX Electronics Corporation 功能描述: |
| AX88772BLI | 制造商:ASIX Electronics Corporation 功能描述: |
| AX88772C | 制造商:ASIX 制造商全稱:ASIX 功能描述:AX88796C -- 低功耗 SPI或Non-PCI以太網(wǎng)控制器與方案 |
| AX88772CLF | 制造商:ASIX Electronics Corporation 功能描述: |
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