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參數(shù)資料
| 型號： | AX88180 |
| 廠商： | ASIX Electronics Corporation |
| 英文描述： | High-Performance Non-PCI 32-bit 10/100/1000M Gigabit Ethernet Controller |
| 中文描述： | 高性能非PCI 32位10/100/1000千兆以太網(wǎng)控制器 |
| 文件頁數(shù)： | 21/47頁 |
| 文件大?。?/td> | 420K |
| 代理商： | AX88180 |
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AX88180
21
ASIX ELECTRONICS CORPORATION
4.12 RXCURT--RX Current Pointer Register
Offset Address = 0xFC34 Default = 0x0000_0000
Field
Name
Type
Default
31:11
-
R
All 0’s
10:0
RXCURPTR
R/W
All 0’s
Description
Reserved
RX Line Current Pointer.
Point to the last line that will be written by hardware. The unit of line is 16
bytes. AX88180 will maintain this register.
4.13 RXBOUND--RX Boundary Pointer Register
Offset Address = 0xFC38 Default = 0x0000_07FF
Field
Name
Type
Default
31:11
-
R
All 0’s
10:0
RXBUNPTR
R/W
0x7FF
Description
Reserved
RX Line Boundary Pointer.
Point to the last line that has been read by driver. The unit of line is 16
bytes.
When driver finished reading packet from RX buffer, it must update this
field.
4.14 MAC_CFG0--MAC Configuration0 Register
Offset Address = 0xFC40 Default = 0x0000_8157
Field
Name
Type
Default
31:16
-
R
All 0’s
15
SPEED100
R/W
1
Description
Reserved
Line Speed Mode
When this bit is enabled and bit12 of MAC_CFG1 is disabled, MAC will
operate in 100Mbps mode otherwise it operates in 10Mbps speed. If bit12
of MAC_CFG1 is enabled, this bit will be ignored
Reserved, this bit must set to 0 for normal operation
Reserved, this bit must set to 0 for normal operation.
RX Flow Control
If this bit and bit8 of RX_CFG are enabled, MAC will perform flow
control and send pause on/off frame when the available space of receive
buffer is less than the value of RXBTHD0.
1 = enable
0 = disable
Reserved, this bit must set to 0 for normal operation.
Inter Packet Gap (IPG) for 10/100M
This field defines the back-to-back transmit packet gap for 10/100M.
Inter Packet Gap for 1000M
This field defines the back-to-back transmit packet gap for 1000M only.
14
13
12
-
-
R/W
R/W
R/W
0
0
0
RXFLOW
11
10:4
-
R/W 0
R/W
IPG100
0x15
3:0
IPG1000
R/W
0x7
4.15 MAC_CFG1--MAC Configuration1 Register
Offset Address = 0xFC44 Default = 0x0000_6000
Field
Name
Type
Default
31:15
-
R
All 0’s
14
PUSRULE
R/W
1
Description
Reserved
Pause Frame Check Rule
When this bit is set, AX88180 accepts pause frame that DA can be any
value.
1 = don’t check DA field.
0 = check DA is equal to “01 80 C2 00 00 01”
Check CRC of received Packet.
When this bit is enabled, AX88180 will drop any CRC error packet.
13
CRCCHK
R/W
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AX88190P | 10/100BASE PCMCIA Fast Ethernet MAC Controller |
| AX88195P | 10/100BASE Local CPU Bus Fast Ethernet MAC Controller |
| AX88196BLF | Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller with MII Interface |
| AX88658AB | 8-Port 10/100/1000BASE-T Ethernet Switch |
| AX88772_07 | USB to 10/100 Fast Ethernet/HomePNA Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AX88180LF | 制造商:ASIX 功能描述:NON PCI MAC CONTROLLER 10/100/1000 |
| AX88190 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCMCIA Fast Ethernet MAC Controller |
| AX88190AL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCMCIA Fast Ethernet MAC Controller |
| AX88190P | 制造商:ASIX 制造商全稱:ASIX 功能描述:10/100BASE PCMCIA Fast Ethernet MAC Controller |
| AX88195P | 制造商:ASIX 制造商全稱:ASIX 功能描述:10/100BASE Local CPU Bus Fast Ethernet MAC Controller |
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