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ASIX ELECTRONICS CORPORATION
6
AX88772A/AX88172A
Low-pin-count
USB 2.0 to 10/100M Fast Ethernet Controller
Table of Contents
1.0
INTRODUCTION
...................................................................................................................9
1.1
G
ENERAL
D
ESCRIPTION
.......................................................................................................................................9
1.2
B
LOCK
D
IAGRAM
................................................................................................................................................9
1.3
P
INOUT
D
IAGRAM
..............................................................................................................................................10
2.0
SIGNAL DESCRIPTION
...........................................................................................14
2.1
AX88772A 64-
PIN
P
INOUT
D
ESCRIPTION
.........................................................................................................14
2.2
AX88172A 80-
PIN
P
INOUT
D
ESCRIPTION
.........................................................................................................16
2.3
H
ARDWARE
S
ETTING
F
OR
O
PERATION
M
ODE
A
ND
M
ULTI
-F
UNCTION
P
INS
......................................................20
3.0
FUNCTION DESCRIPTION
.................................................................................20
3.1
USB C
ORE AND
I
NTERFACE
..............................................................................................................................20
3.2
10/100M E
THERNET
PHY.................................................................................................................................20
3.3
MAC C
ORE
.......................................................................................................................................................20
3.4
O
PERATION
M
ODE
.............................................................................................................................................20
3.5
S
TATION
M
ANAGEMENT
(STA).........................................................................................................................20
3.6
M
EMORY
A
RBITER
............................................................................................................................................20
3.7
USB
TO
E
THERNET
B
RIDGE
..............................................................................................................................20
3.8
S
ERIAL
EEPROM L
OADER
...............................................................................................................................20
3.9
G
ENERAL
P
URPOSE
I/O......................................................................................................................................20
3.10
S
ERIAL
I
NTERFACE
C
ONTROLLER
......................................................................................................................20
3.11
C
LOCK
G
ENERATION
.........................................................................................................................................20
3.12
R
ESET
G
ENERATION
..........................................................................................................................................20
3.13
V
OLTAGE
R
EGULATOR
......................................................................................................................................20
4.0
SERIAL EEPROM MEMORY MAP
........................................................20
4.1
D
ETAILED
D
ESCRIPTION
....................................................................................................................................20
5.0
USB CONFIGURATION STRUCTURE
..............................................20
5.1
USB C
ONFIGURATION
.......................................................................................................................................20
5.2
USB I
NTERFACE
................................................................................................................................................20
5.3
USB E
NDPOINTS
...............................................................................................................................................20
6.0
USB COMMANDS
...............................................................................................................20
6.1
USB S
TANDARD
C
OMMANDS
............................................................................................................................20
6.2
USB V
ENDOR
C
OMMANDS
................................................................................................................................20
6.2.1
Detailed Register Description ..................................................................................................................20
6.2.2
Command Block Wrapper for Serial Interface.........................................................................................20
6.2.2.1
UART controller
.................................................................................................................................20
6.2.2.2
I2C controller
......................................................................................................................................21
6.2.2.3
SPI controller
......................................................................................................................................21
6.3
I
NTERRUPT
E
NDPOINT
.......................................................................................................................................21
7.0
EMBEDDED ETHERNET PHY REGISTER
DESCRIPTION
........................................................................................................................................21
7.1
PHY R
EGISTER
D
ETAILED
D
ESCRIPTION
...........................................................................................................21
7.1.1
Basic Mode Control Register (BMCR).....................................................................................................21
7.1.2
Basic Mode Status Register (BMSR).........................................................................................................21
7.1.3
PHY Identifier Register 1..........................................................................................................................21