參數(shù)資料
型號： AX88141
廠商： ASIX Electronics Corporation
英文描述： 100BASE-TX/FX PCI BUS FAST ETHERNET MAC CONTROLLER WITH POWER MANAGEMENT
中文描述： 100BASE-TX/FX PCI總線的快速以太網(wǎng)MAC控制器電源管理
文件頁數(shù)： 10/43頁
文件大?。?/td> 308K
代理商： AX88141
AX88141 PRELIMINARY
ASIX ELECTRONICS CORPORATION
10
CONFIDENTIAL
2.0 Signal Description
2.1 Signal Descriptions
The following terms describe the AX88141 pin-out:
Address phase
Address and appropriate bus commands are driven during this cycle.
Data phase
Data and the appropriate byte enable codes are driven during this cycle.
#
All pin names with the # suffix are asserted low.
l
l
l
The following abbreviations are used in
Tab - 1 PCI interface group
Tab - 2 Boot ROM , Serial ROM , General-
purpose signals group
,Tab -
3 MII interface signals group
,Tab -
4 Power pins group
..
I
O
I/O
O/D
Input
Output
Input /Output
Open Drain
2.2 PCI interface group
SIGNAL
TYPE
PIN
NUMBER
21,
38,
48,
61
42
DESCRIPTION
CBE#<3>
CBE#<2>
CBE#<1>
CBE#<0>
DEVSEL#
I/O
BUS COMMAND and BYTE ENABLE Are multiplexed on the same PCI pins. During the address
phase of the transaction, CBE#<3:0> Provide the BUS COMMAND. During the data phase,
CBE#<3:0> Provide the BYTE ENABLE. The BYTE ENABLE determines which byte lines carry
valid data., CBE#<0> Applies to byte 0, and CBE#<3> Applies to byte 3.
Device select Is asserted by the target of the current bus access. When the AX88141 is the master of the
current bus access, the target assert DEVSEL# confirming the access. It is driven by AX88141 When
AX88141 is selected as a slave.
The FRAME# Signal is driven by the AX88141 To indicate the beginning and duration of an access.
FRAME# Asserts to indicate the beginning of a bus transaction. While FRAME# is asserted, data
transfers continue. When FRAME# deasserts the next data phase is the final data phase transaction.
BUS GRANT Indicates to the AX88141 That access to the bus is granted.
I/O
FRAME#
I/O
39
GNT#
I
7
IDSEL
I
22
Initialization devise select asserts To indicate that the host is issuing a configuration cycle to the
AX88141.
Interrupt request asserts When one of the appropriate bits of reg5 sets and causes an interrupt, provided
that the corresponding mask bit in reg7 is not asserted. interrupt request deasserts by writing a 1 into the
appropriate reg5 bit.
This pin must be pulled up by an external resistor.
Initiator ready Indicates the bus master
ability to complete the current data phase of the transaction.
A data phase is completed on any rising edge of the clock When both IRDY# and target ready TRDY#
are asserted. Wait cycles are inserted until both IRDY# and TRDY# are asserted together.
When the AX88141 is the bus master, IRDY# is asserted during write operations to indicate that valid
data is present on the AD<31:0>. During read operations, the AX88141 asserts IRDY# to indicate that
it is ready to accept data.
Parity is an even parity bit for the AD<31:0> AD and CBE#<3:0>.
During address and data phases, parity is calculated on all the AD<31:0> AND CBE#<3:0>lines
whether or not any of these lines carry meaningful information.
INT#
O/D
1
IRDY#
I/O
40
PAR
I/O
47
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相關代理商/技術參數(shù)
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AX88172ATF 制造商:ASIX 制造商全稱:ASIX 功能描述:USB 2.0 to 10/100M Fast Ethernet Controller
AX88172L 制造商:ASIX 制造商全稱:ASIX 功能描述:USB to Fast Ethernet/HomePNA Controller
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