參數(shù)資料
型號: ATTINY2313A-SUR
廠商: Atmel
文件頁數(shù): 99/172頁
文件大?。?/td> 0K
描述: MCU AVR 2KB FLASH 20MHZ 20SOIC
產品培訓模塊: tinyAVR Introduction
標準包裝: 1,000
系列: AVR® ATtiny
核心處理器: AVR
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 18
程序存儲器容量: 2KB(1K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 128 x 8
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
包裝: 帶卷 (TR)
其它名稱: ATTINY2313A-SUR-ND
32
8246B–AVR–09/11
ATtiny2313A/4313
6.4
Clock Output Buffer
The device can output the system clock on the CKOUT pin. To enable this, the CKOUT fuse has
to be programmed. This mode of operation is useful when the chip clock is needed to drive other
circuits in the system.
Note that the clock will not be output during reset and that the normal operation of the I/O pin will
be overridden when the fuse is programmed. Any clock source, including the internal RC Oscil-
lator, can be selected when the clock is output on CKOUT pin.
If the System Clock Prescaler is used, it is the divided system clock that is output.
6.5
Register Description
6.5.1
OSCCAL – Oscillator Calibration Register
Bit 7 – Res: Reserved Bit
This bit is reserved bit in ATtiny2313A/4313 and it will always read zero.
Bits 6:0 – CAL[6:0]: Oscillator Calibration Value
Writing the calibration byte to this address will trim the internal Oscillator to remove process vari-
ations from the Oscillator frequency. This is done automatically during Chip Reset. When
OSCCAL is zero, the lowest available frequency is chosen. Writing non-zero values to this regis-
ter will increase the frequency of the internal Oscillator. Writing 0x7F to the register gives the
highest available frequency.
The calibrated Oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is
written, do not calibrate to more than 10% above the nominal frequency. Otherwise, the
EEPROM or Flash write may fail. Note that the Oscillator is intended for calibration to 8 MHz or 4
MHz. Tuning to other values is not guaranteed, as indicated in Table 6-8 below.
To ensure stable operation of the MCU the calibration value should be changed in small steps. A
variation in frequency of more than 2% from one cycle to the next can lead to unpredicatble
behavior. Changes in OSCCAL should not exceed 0x20 for each calibration. It is required to
ensure that the MCU is kept in Reset during such changes in the clock frequency.
6.5.2
CLKPR – Clock Prescale Register
Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE
bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is
cleared by hardware four cycles after it is written or when the CLKPS bits are written. Rewriting
Bit
765
4321
0
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
OSCCAL
Read/Write
R
R/W
Initial Value
0
Device Specific Calibration Value
Bit
7
6
5
4
3
2
1
0
CLKPCE
CLKPS3
CLKPS2
CLKPS1
CLKPS0
CLKPR
Read/Write
R/W
R
R/W
Initial Value
0
See Bit Description
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