參數(shù)資料
型號: ATTINY13V-10SSUR
廠商: Atmel
文件頁數(shù): 173/176頁
文件大?。?/td> 0K
描述: MCU AVR 1KB FLASH 10MHZ 8SOIC
產(chǎn)品培訓(xùn)模塊: tinyAVR Introduction
標準包裝: 4,000
系列: AVR® ATtiny
核心處理器: AVR
芯體尺寸: 8-位
速度: 10MHz
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 6
程序存儲器容量: 1KB(512 x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 64 x 8
RAM 容量: 64 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
包裝: 帶卷 (TR)
其它名稱: ATTINY13V-10SSUR-ND
ATTINY13V-10SSURTR
PIC16(L)F720/721
DS41430C-page 96
Preliminary
2010-2011 Microchip Technology Inc.
13.1
Timer1 Operation
The Timer1 module is a 16-bit incrementing counter
which is accessed through the TMR1H:TMR1L register
pair. Writes to TMR1H or TMR1L directly update the
counter.
When used with an internal clock source, the module is
a timer and increments on every instruction cycle.
When used with an external clock source, the module
can be used as either a timer or counter and
increments on every selected edge of the external
source.
Timer1 is enabled by configuring the TMR1ON and
TMR1GE bits in the T1CON and T1GCON registers,
respectively. Table 13-1 displays the Timer1 enable
selections.
13.2
Clock Source Selection
The TMR1CS<1:0> bits of the T1CON register are used
to select the clock source for Timer1. Table 13-2 displays
the clock source selections.
13.2.1
INTERNAL CLOCK SOURCE
When the internal clock source is selected the
TMR1H:TMR1L register pair will increment on multiples
of FOSC as determined by the Timer1 prescaler.
13.2.2
EXTERNAL CLOCK SOURCE
When the external clock source is selected, the Timer1
module may work as a timer or a counter. When enabled
to count, Timer1 is incremented on the rising edge of the
external clock input T1CKI.
TABLE 13-2:
CLOCK SOURCE
SELECTIONS
TABLE 13-1:
TIMER1 ENABLE
SELECTIONS
TMR1ON
TMR1GE
Timer1
Operation
00
Off
01
Off
10
Always On
11
Count Enabled
Note:
In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge after any one or
more of the following conditions:
Timer1 enabled after POR Reset
Write to TMR1H or TMR1L
Timer1 is disabled
Timer1 is disabled (TMR1ON = 0)
when T1CKI is high then Timer1 is
enabled (TMR1ON=1) when T1CKI is
low.
TMR1CS<1:0>
Clock Source
01
System Clock (FOSC)
00
Instruction Clock (FOSC/4)
10
External Clocking on T1CKI Pin
11
Reserved
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