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參數(shù)資料
| 型號(hào)： | ATF22LV10C-15SI |
| 廠商： | Atmel |
| 文件頁(yè)數(shù)： | 17/19頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PLD EE 15NS 24-SOIC |
| 標(biāo)準(zhǔn)包裝： | 31 |
| 系列： | 22V10 |
| 可編程類型： | EE PLD |
| 宏單元數(shù)： | 10 |
| 輸入電壓： | 3.3V |
| 速度： | 15ns |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC W |
| 包裝： | 管件 |
| 其它名稱： | ATF22LV10C15SI |
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7
0780M–PLD–7/10
Atmel ATF22LV10C
8.
Power-down Mode
The Atmel ATF22LV10C includes an optional pin controlled power-down feature. When this mode is enabled, the
PD pin acts as the power-down pin (Pin 4 on the DIP/SOIC packages and Pin 5 on the PLCC package). When the
PD pin is high, the device supply current is reduced to less than 100mA. During power-down, all output data and
internal logic states are latched and held. Therefore, all registered and combinatorial output data remain valid. Any
outputs which were in an undetermined state at the onset of power-down will remain at the same state. During
power-down, all input signals except the power-down pin are blocked. Input and I/O hold latches remain active to
insure that pins do not float to indeterminate levels, further reducing system power. The power-down pin feature is
enabled in the logic design file. Designs using the power-down pin may not use the PD pin logic array input.
However, all other PD pin macrocell resources may still be used, including the buried feedback and foldback
product term array inputs.
PD pin configuration is controlled by the design file, and appears as a separate fuse bit in the JEDEC file. When
the power-down feature is not specified in the design file, the IN/PD pin will be configured as a regular logic input.
Note:
Some programmers list the 22V10 JEDEC-compatible 22V10C (no PD used) separately from the non-22V10 JEDEC-
compatible 22V10CEX (with PD used).
Figure 8-1.
Input Diagram
Figure 8-2.
I/O Diagram
ESD
PROTECTION
CIRCUIT
VCC
INPUT
100K
VCC
100K
INPUT
OE
DATA
VCC
I/O
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|---|---|
| ATF22LV10C-15XC | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 500 GATE STANDARD POWER 3.3V - 15NS RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ATF22LV10C-15XI | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 ASICS RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ATF22LV10CQZ | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High-performance Electrically Erasable Programmable Logic Device |
| ATF22LV10CQZ-30JC | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 500 GT 3.3-5V SPLY ZERO/QRTR PWR-30NS RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ATF22LV10CQZ-30JI | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 EEPLD 500 GATE 3.3 5V PWR 30NS IND TEMP RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
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