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參數(shù)資料
| 型號： | AT91M42800A-33CJ-999 |
| 廠商： | Atmel |
| 文件頁數(shù)： | 6/27頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 32BIT RISC 144BGA |
| 標準包裝： | 1 |
| 系列： | AT91 |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 33MHz |
| 連通性： | EBI/EMI，SPI，UART/USART |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 54 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 144-LFBGA |
| 包裝： | 剪切帶 (CT) |
| 其它名稱： | AT91M42800A-33CJ-999CT |
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14
1779ES–ATARM–14-Apr-06
AT91M42800A
7.6.3
IEEE 1149.1 JTAG Boundary Scan
IEEE 1149.1 JTAG Boundary Scan is enabled when MODE0 is low and MODE1 is high. The
functions SAMPLE, EXTEST and BYPASS are implemented. In ICE Debug mode, the ARM
core responds with a non-JTAG chip ID that identifies the core to the ICE system. This is not
IEEE 1149.1 JTAG compliant. It is not possible to switch directly between JTAG and ICE opera-
tions. A chip reset must be performed (NRST and NTRST) after MODE0 and MODE1 are
changed.
7.7
Memory Controller
The ARM7TDMI processor address space is 4G bytes. The memory controller decodes the
internal 32-bit address bus and defines three address spaces:
Internal Memories in the four lowest megabytes
Middle Space reserved for the external devices (memory or peripherals) controlled by the
EBI
Internal Peripherals in the four highest megabytes
In any of these address spaces, the ARM7TDMI operates in little-endian mode only.
7.7.1
Protection Mode
The embedded peripherals can be protected against unwanted access. The PME (Protect Mode
Enable) pin must be tied high and validated in its peripheral operation (PIO Disable) to enable
the protection mode. When enabled, any peripheral access must be done while the ARM7TDMI
is running in Privileged mode (i.e., the accesses in user mode result in an abort). Only the valid
peripheral address space is protected and requests to the undefined addresses will lead to a
normal operation without abort.
7.7.2
Internal Memories
The AT91M42800A microcontroller integrates an 8-Kbyte primary internal SRAM. All internal
memories are 32 bits wide and single-clock cycle accessible. Byte (8-bit), half-word (16-bit) or
word (32-bit) accesses are supported and are executed within one cycle. Fetching Thumb or
ARM instructions is supported and internal memory can store twice as many Thumb instructions
as ARM ones.
The SRAM bank is mapped at address 0x0 (after the remap command), and ARM7TDMI excep-
tion vectors between 0x0 and 0x20 that can be modified by the software. The rest of the bank
can be used for stack allocation (to speed up context saving and restoring), or as data and pro-
gram storage for critical algorithms.
7.7.3
Boot Mode Select
The ARM reset vector is at address 0x0. After the NRST line is released, the ARM7TDMI exe-
cutes the instruction stored at this address. This means that this address must be mapped in
nonvolatile memory after the reset.
The input level on the BMS pin during the last 10 SLCK clock cycles before the rising edge of the
NRST selects the type of boot memory. The Boot mode depends on BMS (see Table 7-1).
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