參數(shù)資料
型號： AT89LP214-20XU
廠商： Atmel
文件頁數(shù)： 67/98頁
文件大?。?/td> 0K
描述： MCU 8051 2K FLASH 20MHZ 14-TSSOP
產(chǎn)品培訓模塊： MCU Product Line Introduction
標準包裝： 95
系列： 89LP
核心處理器： 8051
芯體尺寸： 8-位
速度： 20MHz
連通性： SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 12
程序存儲器容量： 2KB（2K x 8）
程序存儲器類型： 閃存
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 2.4 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 14-TSSOP（0.173"，4.40mm 寬）
包裝： 管件
7
3538E–MICRO–11/10
AT89LP213/214
5.6
Watchdog Timer
The Watchdog Timer in AT89LP213/214 counts at a rate of once per clock cycle. This compares
to once every 12 clocks in the standard 8051. A common prescaler is available to divide the time
base for all timers and reduce the counting rate.
5.7
I/O Ports
The I/O ports of the AT89LP213/214 may be configured in four different modes. By default all
the I/O ports revert to input-only (tristated) mode at power-up or reset. In the standard 8051, all
ports are weakly pulled high during power-up or reset. To enable 8051-like ports, the ports must
be put into quasi-bidirectional mode by clearing the P1M0 and P3M0 SFRs. The user can also
configure the ports to start in quasi-bidirectional mode by disabling the Tristate-Port User Fuse.
When this fuse is disabled, P1M0 and P3M0 will reset to 00h instead of FFh and the ports will be
weakly pulled high.
5.8
Reset
The RST pin of the AT89LP213/214 is active-low as compared with the active high reset in the
standard 8051. In addition, the RST pin is sampled every clock cycle and must be held low for a
minimum of two clock cycles, instead of 24 clock cycles, to be recognized as a valid reset.
6.
Memory Organization
The AT89LP213/214 uses a Harvard Architecture with separate address spaces for program
and data memory. The program memory has a regular linear address space with support for up
to 64K bytes of directly addressable application code. The data memory has 128 bytes of inter-
nal RAM and 128 bytes of Special Function Register I/O space. The AT89LP213/214 does not
support external data memory or external program memory.
6.1
Program Memory
The AT89LP213/214 contains 2K bytes of on-chip In-System Programmable Flash memory for
program storage. The Flash memory has an endurance of at least 10,000 write/erase cycles and
a minimum data retention time of 10 years. The reset and interrupt vectors are located within the
first 59 bytes of program memory (refer to Table 12-1 on page 20). Constant tables can be allo-
cated within the entire 2K program memory address space for access by the MOVC instruction.
The AT89LP213/214 does not support external program memory.
Figure 6-1.
Program Memory Map
Program Memory
0000
07FF
0000
001F
Atmel Signature Array
0040
007F
User Signature Array
相關(guān)PDF資料
PDF描述
VE-B5X-IW-F2 CONVERTER MOD DC/DC 5.2V 100W
V375A36E500BF3 CONVERTER MOD DC/DC 36V 500W
AT89LP213-20XU MCU 8051 2K FLASH 20MHZ 14-TSSOP
V375A36E500BF2 CONVERTER MOD DC/DC 36V 500W
V375A36E500BF CONVERTER MOD DC/DC 36V 500W
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