參數(shù)資料
型號(hào): AT89EB5114-TGSIL
廠商: Atmel
文件頁數(shù): 21/86頁
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 4K 20SOIC
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
標(biāo)準(zhǔn)包裝: 38
系列: 89EB
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 11
程序存儲(chǔ)器容量: 4KB(4K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 6x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 616 (CN2011-ZH PDF)
28
AT89/83EB5114
4311C–8051–02/08
Registers
Table 13. TCON (S:88h)
Timer/Counter Control Register
Reset Value = 0000 0000b
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Bit
Number
Bit
Mnemonic Description
7
TF1
Timer 1 Overflow flag
Cleared by the hardware when processor vectors to interrupt routine.
Set by the hardware on Timer 1 register overflows.
6
TR1
Timer 1 Run Control bit
Clear to turn off Timer/Counter 1.
Set to turn on Timer/Counter 1.
5
TF0
Timer 0 Overflow flag
Cleared by the hardware when processor vectors to interrupt routine.
Set by the hardware on Timer 0 register overflows.
4
TR0
Timer 0 Run Control bit
Clear to turn off Timer/Counter 0.
Set to turn on Timer/Counter 0.
3
IE1
Interrupt 1 Edge flag
Cleared by the hardware as soon as the interrupt is processed.
Set by the hardware when external interrupt is detected on the INT1 pin.
2
IT1
Interrupt 1 Type Control bit
Clear to select low level active for external interrupt 1 (INT1).
Set to select sensitive edge trigger for external interrupt 1. The sensitive edge
(Rising or Falling) is determined by ESB1 value (Edge Selection Bit 1) in IOR
(Interrupt Option Register).
1
IE0
Interrupt 0 Edge flag
Cleared by the hardware as soon as the interrupt is processed.
Set by the hardware when external interrupt is detected on INT0 pin.
0
IT0
Interrupt 0 Type Control bit
Clear to select low level active trigger for external interrupt 0 (INT0).
Set to select sensitive edge trigger for external interrupt 0. The sensitive edge
(Rising or Falling) is determined by ESB0 (Edge Selection Bit 0) in IOR (Interrupt
Option Register).
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