參數(shù)資料
型號: AT89C51IC2-SLSIL
廠商: Atmel
文件頁數(shù): 80/140頁
文件大小: 0K
描述: IC 8051 MCU FLASH 32K 44PLCC
標準包裝: 27
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 34
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 1.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
44
AT89C51IC2
4301D–8051–02/08
Figure 14. PCA Compare Mode and PCA Watchdog Timer
Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value,
otherwise an unwanted match could happen. Writing to CCAPnH will set the ECOM bit.
Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t
occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this
reason, user software should write CCAPnL first, and then CCAPnH. Of course, the
ECOM bit can still be controlled by accessing to CCAPMn register.
High Speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle
each time a match occurs between the PCA counter and the module's capture registers.
To activate this mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR
must be set (See Figure 15).
A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit.
CH
CL
CCAPnH
CCAPnL
ECOMn
CCAPMn, n = 0 to 4
0xDA t o 0xDE
CAPNn MATn TOGn PWMn ECCFn
CAPPn
16 bit comparator
Match
CCON
0xD8
PCA I T
Enable
PCA counter/ timer
RESET *
CIDL
CPS1 CPS0
ECF
CMOD
0xD9
WDTE
Reset
Write to
CCAPnL
Write t o
CCAPnH
CF
CCF2 CCF1 CCF0
CR
CCF3
CCF4
1
0
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