參數(shù)資料
型號(hào)： AT89C51IC2-SLSIL
廠商： Atmel
文件頁數(shù)： 117/140頁
文件大?。?/td> 0K
描述： IC 8051 MCU FLASH 32K 44PLCC
標(biāo)準(zhǔn)包裝： 27
系列： 89C
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 34
程序存儲(chǔ)器容量： 32KB（32K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 1.25K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-LCC（J 形引線）
包裝： 管件
78
AT89C51IC2
4301D–8051–02/08
Reset Value = 0001 0100b
Not bit addressable
Serial Peripheral Status Register
(SPSTA)
The Serial Peripheral Status Register contains flags to signal the following conditions:
Data transfer complete
Write collision
Inconsistent logic level on SS pin (mode fault error)
Table 59 describes the SPSTA register and explains the use of every bit in the register.
Table 59. SPSTA Register
SPSTA - Serial Peripheral Status and Control register (0C4H)
1
SPR1
SPR2
SPR1
SPR0 Serial Peripheral Rate
0
F
CLK PERIPH /2
0
1
F
CLK PERIPH /4
0
1
0
F
CLK PERIPH /8
0
1
F
CLK PERIPH /16
1
0
F
CLK PERIPH /32
1
0
1
F
CLK PERIPH /64
1
0
F
CLK PERIPH /128
1
Invalid
0
SPR0
Bit Number
Bit Mnemonic
Description
7
6
5
4
3
2
1
0
SPIF
WCOL
SSERR
MODF
-
Bit
Number
Bit
Mnemonic Description
7
SPIF
Serial Peripheral Data Transfer Flag
Cleared by hardware to indicate data transfer is in progress or has been
approved by a clearing sequence.
Set by hardware to indicate that the data transfer has been completed.
6
WCOL
Write Collision Flag
Cleared by hardware to indicate that no collision has occurred or has been
approved by a clearing sequence.
Set by hardware to indicate that a collision has been detected.
5
SSERR
Synchronous Serial Slave Error Flag
Set by hardware when SS is deasserted before the end of a received data.
Cleared by disabling the SPI (clearing SPEN bit in SPCON).
4
MODF
Mode Fault
Cleared by hardware to indicate that the SS pin is at appropriate logic level, or
has been approved by a clearing sequence.
Set by hardware to indicate that the SS pin is at inappropriate logic level.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit
2
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
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