參數(shù)資料
型號: AT89C5131A-PUTIM
廠商: Atmel
文件頁數(shù): 36/176頁
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 32K USB 32QFN
標準包裝: 260
系列: AT89C513x
核心處理器: C52X2
芯體尺寸: 8-位
速度: 48MHz
連通性: I²C,SPI,UART/USART,USB
外圍設備: LED,POR,PWM,WDT
輸入/輸出數(shù): 18
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量: 1.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 32-VQFN 裸露焊盤
包裝: 托盤
配用: AT89STK-10-ND - KIT EVAL APPL MASS STORAGE
AT89STK-05-ND - KIT STARTER FOR AT89C5131
128
AT89C5131
4136C–USB–04/05
Miscellaneous
USB Reset
The EORINT bit in the USBINT register is set by hardware when a End Of Reset has
been detected on the USB bus. This triggers a USB interrupt if enabled. The USB con-
troller is still enabled, but all the USB registers are reset by hardware. The firmware will
clear the EORINT bit to allow the next USB reset detection.
STALL Handshake
This function is only available for Control, Bulk, and Interrupt endpoints.
The firmware has to set the STALLRQ bit in the UEPSTAX register to send a STALL
handshake at the next request of the Host on the endpoint selected with the UEPNUM
register. The RXSETUP, TXRDY, TXCMPL, RXOUTB0 and RXOUTB1 bits must be first
reset to 0. The bit STLCRC is set at 1 by the USB controller when a STALL has been
sent. This triggers an interrupt if enabled.
The firmware will clear the STALLRQ and STLCRC bits after each STALL sent.
The STALLRQ bit is cleared automatically by hardware when a valid SETUP PID is
received on a CONTROL type endpoint.
Important note: when a Clear Halt Feature occurs for an endpoint, the firmware will reset
this endpoint using the UEPRST register in order to reset the data toggle management.
Start of Frame Detection
The SOFINT bit in the USBINT register is set when the USB controller detects a Start of
Frame PID. This triggers an interrupt if enabled. The firmware will clear the SOFINT bit
to allow the next Start of Frame detection.
Frame Number
When receiving a Start of Frame, the frame number is automatically stored in the
UFNUML and UFNUMH registers. The CRCOK and CRCERR bits indicate if the CRC of
the last Start of Frame is valid (CRCOK set at 1) or corrupted (CRCERR set at 1). The
UFNUML and UFNUMH registers are automatically updated when receiving a new Start
of Frame.
Data Toggle Bit
The Data Toggle bit is set by hardware when a DATA0 packet is received and accepted
by the USB controller and cleared by hardware when a DATA1 packet is received and
accepted by the USB controller. This bit is reset when the firmware resets the endpoint
FIFO using the UEPRST register.
For Control endpoints, each SETUP transaction starts with a DATA0 and data toggling
is then used as for Bulk endpoints until the end of the Data stage (for a control write
transfer). The Status stage completes the data transfer with a DATA1 (for a control read
transfer).
For Isochronous endpoints, the device firmware will ignore the data-toggle.
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