![](http://datasheet.mmic.net.cn/Atmel/AT87F52-24PC_datasheet_96437/AT87F52-24PC_20.png)
Not
20
Serial Port Timing: Shift Register Mode Test Conditions
The values in this table are valid for VCC = 5.0V ± 20% and Load Capacitance = 80 pF.
Shift Register Mode Timing Waveforms
Symbol
Parameter
12 MHz Osc
Variable Oscillator
Units
Min
Max
Min
Max
tXLXL
Serial Port Clock Cycle Time
1.0
12tCLCL
s
tQVXH
Output Data Setup to Clock Rising Edge
700
10tCLCL-133
ns
tXHQX
Output Data Hold After Clock Rising Edge
50
2tCLCL-117
ns
tXHDX
Input Data Hold After Clock Rising Edge
0
ns
tXHDV
Clock Rising Edge to Input Data Valid
700
10tCLCL-133
ns
t
XHDV
t
QVXH
t
XLXL
t
XHDX
t
XHQX
ALE
INPUT DATA
CLEAR RI
OUTPUT DATA
WRITE TO SBUF
INSTRUCTION
CLOCK
0
1
2
3
4
5
6
7
SET TI
SET RI
8
VALID
Float Waveforms(1)
Note:
1.
For timing purposes, a port pin is no longer floating
when a 100 mV change from load voltage occurs. A
port pin begins to float when a 100 mV change from
the loaded VOH/VOL level occurs.
V
LOAD
+ 0.1V
Timing Reference
Points
V
LOAD
- 0.1V
LOAD
V
OL
+ 0.1V
V
OL
- 0.1V
AC Testing Input/Output Waveforms(1)
Note:
1.
AC Inputs during testing are driven at VCC - 0.5V
for a logic 1 and 0.45V for a logic 0. Timing mea-
surements are made at VIH min. for a logic 1 and VIL
max. for a logic 0.
0.45V
TEST POINTS
V
- 0.5V
CC
0.2 V
+ 0.9V
CC
0.2 V
- 0.1V
CC