TA = 0
參數(shù)資料
型號： AT80C51RD2-RLRUM
廠商： Atmel
文件頁數(shù)： 61/81頁
文件大?。?/td> 0K
描述： IC MCU 80C51 HI PERFORM 44VQFP
產(chǎn)品培訓模塊： MCU Product Line Introduction
標準包裝： 1
系列： 80C
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲器類型： ROMless
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-LQFP
包裝： 標準包裝
其它名稱： AT80C51RD2-RLRUMDKR
61
4113D–8051–01/09
AT80C51RD2
17.2
DC Parameters for Standard Voltage (2)
TA = 0
°C to +70°C; V
SS = 0 V; VCC = 2.7V to 5.5V; F = 10 to 40 MHz
TA = -40
°C to +85°C; V
SS = 0 V; VCC = 2.7V to 5.5V; F = 10 to 40 MHz
Notes:
1. Operating I
CC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 17-4.),
V
IL = VSS + 0.5V,
VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used (see Figure
2. Idle I
CC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5V,
VIH = VCC - 0.5V; XTAL2 N.C; Port 0 = VCC; EA = RST = VSS (see Figure 17-2).
3. Power-down I
CC is measured with all output pins disconnected; EA = VSS, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Figure
4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1
and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0
transitions during bus operation. In the worst cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed
0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary.
5. Typical are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and
5V.
6. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum I
OL per port pin: 10 mA
Maximum I
OL per 8-bit port:
Port 0: 26 mA
Ports 1, 2 and 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
7. For other values, please contact your sales office.
Symbol
Parameter
Min
Typ(5)
Max
Unit
Test Conditions
V
IL
Input Low Voltage
-0.5
0.2 V
CC - 0.1
V
IH
Input High Voltage except XTAL1, RST
0.2 V
CC + 0.9
V
CC + 0.5
V
IH1
Input High Voltage, XTAL1, RST
0.7 V
CC
V
CC + 0.5
V
OL
Output Low Voltage, ports 1, 2, 3, 4 and 5 (6)
0.45
V
I
OL = 0.8 mA
(4)
V
OL1
Output Low Voltage, port 0, ALE, PSEN (6)
0.45
V
I
OL = 1.6 mA
(4)
V
OH
Output High Voltage, ports 1, 2, 3, 4 and 5
0.9 V
CC
VI
OH = -10 μA
V
OH1
Output High Voltage, port 0, ALE, PSEN
0.9 V
CC
VI
OH = -40 μA
I
IL
Logical 0 Input Current ports 1, 2, 3, 4 and 5
-50
μAV
IN = 0.45V
I
LI
Input Leakage Current
±10
μA
0.45V < V
IN < VCC
I
TL
Logical 1 to 0 Transition Current, ports 1, 2, 3, 4
and 5
-650
μAV
IN = 2.0V
R
RST
RST Pulldown Resistor
50
200
250
k
Ω
CIO
Capacitance of I/O Buffer
10
pF
Fc = 3 MHz
TA = 25
°C
I
PD
Power-down Current
120
150
μAV
CC =2.7V to 5.5V
(3)
I
CCOP
Power Supply Current on normal mode
0.29 x Frequency (MHz) + 4
mA
V
CC = 5.5V
(1)
I
CCIDLE
Power Supply Current on idle mode
0.16 x Frequency (MHz) + 4
mA
V
CC = 5.5V
(2)
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