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參數(shù)資料
| 型號(hào)： | ASM4SSTVF16857-48VT |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | DDR 14-Bit Registered Buffer |
| 中文描述： | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48 |
| 封裝： | 0.173 INCH, 0.40 MM PITCH, TVSOP-48 |
| 文件頁(yè)數(shù)： | 7/16頁(yè) |
| 文件大?。?/td> | 147K |
| 代理商： | ASM4SSTVF16857-48VT |
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August 2004
ASM4SSTVF16857
rev 2.0
DC Electrical Characteristics -PC3200
DDR 14-Bit Registered Buffer
7 of 16
T
A
= 0°C to 70°C, V
DD
= 2.6 ± 0.2V, and V
DDQ
= 2.6±0.2V (unless otherwise stated)
Guaranteed by design. Not 100% production tested.
Symbol
Parameters
Test conditions
V
DD
(V)
Min
Typ
Max
Units
V
IK
I
I
= -18 mA
2.5
-1.2
V
I
OH
= -100
A
2.5 V to 2.7
V
DD
- 0.2
V
V
OH
I
OH
= -8 mA
2.5
1.95
V
I
OL
= 100
A
2.5 V to 2.7
0.2
V
V
OL
I
OL
= 8 mA
2.5
0.35
V
I
I
All inputs
V
I
= V
DD
or GND
2.7
± 5
A
Standby
(static)
RESETB = GND
2.7
0.01
A
I
DD
Operating
(static)
V
I
= V
IH(AC)
or V
IL(AC)
,
RESETB = V
DD
2.7
25
mA
Dynamic
operating
(clock only)
RESETB = V
DD
,
V
I
= V
IH(AC)
or V
IL(AC)
,
CLK and CLKB switching
50% duty cycle
2.7
328
A/clock
MHz
I
DDD
Dynamic
operating (per
each data
input)
RESETB = V
DD
,
V
I
= V
IH(AC)
or V
IL(AC)
,
CLK and CLKB =
switching 50% duty cycle;
One data input switching
at half clock frequency,
50% duty cycle
I
O
= 0
2.7
15
/clock
MHz/data
input
r
OH
Output high
I
OH
= -20 mA
2.5 V to 2.7
7
13.5
20
r
OL
Output low
I
OL
= 20 mA
2.5 V to 2.7
7
20
r
O(D)
|r
OH
- r
OL
| each
separate bit
I
O
= 20 mA, T
A
= 25
C
2.6
4
Data inputs
2.6
2.5
3.5
pF
CLK & CLKB
V
I
= V
REF
± 310 mV, V
ICR
= 1.25 V,
V
I(PP)
= 360 mV
2.6
2.5
3.5
pF
C
i
RESETB
V
I
= V
DD
or GND
2.6
2.5
3.5
pF
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