參數(shù)資料
型號(hào): AS8530A-ASOT
廠商: ams
文件頁(yè)數(shù): 7/33頁(yè)
文件大?。?/td> 0K
描述: IC SYSTEM BASIS CHIP 8-SOIC
標(biāo)準(zhǔn)包裝: 2,500
系列: *
Revision 1.1
14 - 32
AS8530
Datasheet - Detailed Descr i p ti on
7.4 RESET
Reset generates an external RESET signal to reset the microcontroller and all other external circuits. The reset functionality is illustrated in
Figure 4. Reset consists of a digital buffer at the output. RESET signal can be affected by RESET_VCC_N (which is the under-voltage reset on
VCC) and Window watchdog output. All those conditions which cause a drop in the VCC voltage will be detected from the low voltage reset unit,
which in-turn generates a reset signal. States like Temporary shut-down, Over-temperature monitor will influence the RESET output through
RESET_VCC_N signal only.
Figure 4. Reset Functionality
7.5 VCC Undervoltage Reset
The POR-VCC generates RESET_VCC_N signal as output which determines under-voltage reset of the output of the LDO. The rising edge of
the VCC gives an under-voltage reset “off” and the falling edge of the VCC gives an under-voltage reset “on”. This under-voltage signal is used to
control the RESET output. When VCC rises up Vuvr_off for a period greater than reset duration (tRes) then RESET_VCC_N switches from low
level to high level and pin RESET is inactive (high). If VCC falls below Vuvr_on for a period greater than a predetermined delay (trr) then
RESET_VCC_N switches from high level to low level and pin RESET is active (low). The RESET_VCC_N signal is used to initializes Window
watchdog timer, TX time-out, Test control circuits, 2-wire SP, and logic associated with SP (everything other than the SP control registers). VCC
under-voltage reset threshold voltage level adjustment can be made by 2 bit OTP as explained in OTP interface.
7.6 Window Watchdog (WWD)
To keep the external microcontroller always in proper function state, a window watchdog circuit is implemented. The WWD trigger is generated
by external MCU through SP interface. If the window is missed, a reset on the RESET pin with certain reset time (tRes) is generated. The WWD
function can be enabled or disabled by factory setting. The watchdog is started after the ASSP exits reset. Under normal working conditions,
microcontroller gives a WWD trigger every time in the window period of WD_TSV (service time). If the trigger does not occur during WD_TSV or
occurs too early during WD_TCL (non-service time), then RESET output is pulled low (active), which will reset the micro-controller. WWD circuit
is turned on after the RESET pin goes back to high (inactive). If VCC < Vuvr_on, WWD circuit is switched off. When the WWD function is
enabled, there is a 3-bit factory programming available to set the trigger window.
VCC
VSUP
VUVR_OFF
tRes
trr
T>Tj
T<Tj
t<trr
tRes
RESET
Initialization
Thermal shutdown
Spike VSUP
Low voltage VSUP
Current limitation active
VUVR_ON
tRes
MISSING
WATCHDOG
ACCESS
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